MT9072AB datasheet(112/275 Pages) ZARLINK

112 / 275 page

MT9072

Data Sheet

112

Zarlink Semiconductor Inc.

17.1.1.5

Master Status Registers Address (Y10-Y1F) Summary

Binary Address

(A11-A0)

Hex

Address R/W

Control Bits

(B15 - B8 / B7 - B0)

yyyy 0001 0000

Y10

Synchronization and

Alarm Status Word

#, #, TFSYNC,MFSYNC,SE,LOS,D4YALM,D4Y48,

SECYEL,ESFYEL,AIS,PDV,LLED,LLDD,T1DRR,

T1DRY

yyyy 0001 0001

Y11

Timer Status Word

#,#,#,#,#,#,#,#,#,#,#,#,#,1SEC,2SEC,#

yyyy 0001 0010

Y12

Receive Bit Oriented

Message

#,#,#,#,#,#,RxBOM,RxBOMM,RxBOM7-0

yyyy 0001 1011

Y13

Receive Slip Buffer Word #,#,PIR2:0,RSLPD,RXSLIP,RXFRM,

RXTS4-0,RxBC2-0

yyyy 0001 0100

Y14

Transmit Slip Buffer

Word

#,#,#,#,#,TSLIP,TSLPD,TXSBMSB,

TXTS4-0,TXBC2-0

yyyy 0001 0101

Y15

PRBS Error Counter and

CRC Multiframe Counter

for PRBS

PSM7-0,PS7-0

yyyy 0001 0110

Y16

MFOOF

MFOOF15-0

yyyy 0001 0111

Y17

Framing Bit ErrorCounter FC15-0

yyyy 0001 1000

Y18

Bipolar Violation Counter BPV15-0

yyyy 0001 1001

Y19

CRC-6 Error Counter

CC15-0

yyyy 0001 1010

Y1A

OOF and COFA counter OOF7:0,COFA7:0

yyyy 0001 1011

Y1B

Excessive Zero Counter #,#,#,#,#,#,#,#,EXZ7:0

yyyy 0001 1100

Y1C

TX Byte Counter

Position and HDLC Test

Status

#,#,#,#,RXclk,TXclk,Vcrc,Vaddr,TBP7:0

yyyy 0001 1101

Y1D

HDLC Status

#,#,#,#,#,#,#,#,#,IDC,RQ9-8,TXSTAT1-0,

RXSTA1-0

yyyy 0001 1110

Y1E

RX CRC

CRC15-0

yyyy 0001 1111

Y1F

RX FIFO

#,#,#,#,#,#,#,#,RXFIFO7-0

xxxx indicates all (0000 to 1111) binary possibilities

X indicates all (0 to F) hex possibilities

yyyy indicates 9 (000, 001, 010, 011, 111,1000,1001) binary possibilities representing 1 of 8 framers (R/W), and

all 8 framers (W only)

Y indicates 9 (0,1,2,3,4...9) hex possibilities representing 1 of 8 framers (R/W), and all 8 framers (W only)

Table 59 - Master Status Register(R) Address(Y1X) Summary (T1)

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