MT9072AB datasheet(115/275 Pages) ZARLINK

115 / 275 page

MT9072

Data Sheet

115

Zarlink Semiconductor Inc.

17.1.2

Interrupt Mask Registers Address (Y40-Y4F) Summary

17.1.3

Master Control Registers (Y00 to YF0 ) Bit Functions

Tables 64 to 79 describe the bit functions of each of the Master Control Registers in the MT9072. Each register is

repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2 with Y=2,...

Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB) A11 A10 A9 A8). In addition, a

simultaneous write to all 8 Framers is possible by setting the address A11 to 1 and A10 to A8 to 0. A (0), (1) or (#)

in the “Name” column of these tables indicates the state of the data bits after a hard reset (the RESET pin is toggled

from zero to one), or a software reset (the RST bit in control register address YF1 is toggled from one to zero or

toggling of RSTC in Global Control Register). The (#) indicates that a (0) or (1) is possible.

Binary Address

(A11-A0)

Hex

Address R/W

Interrupt Mask

Control Bits

(B15 - B8 / B7 - B0)

yyyy 0010 0000-

yyyy 0010 0010

Y40-Y42

not used

yyyy 0100 0011

Y43

HDLC Interrupt Mask #,#,#,#,#,#,#,GAIM,EOPDIM,TEOPIM,EOPRIM,

TXFLIM,FAIM,TXUNDERIM,RXFFIM,RXOVFLIM

yyyy 0100 0100

Y44

Receive Sync and

Alarm Interrupt Mask

FEOIM,CRCOIM,OOFOIM,COFAOIM,BPVOIM,

PRBSOIM,PRBSMFOIM,MFOOFOIM,TFSYNIM,

MFSYNIM,FBEIM,COFAIM,SEFIM,AISIM,CRCIM,

LOSIM

yyyy 0100 0101

Y45

Receive Line status

and Timer Interrupt

Mask

D4YALMIM,D4Y48IM,SECYELIM,ESFYELIM,

T1DMYIM,#,BPVIM,PRBSIM,PDVIM,LLEDIM,

LLDDIM,BIOMIM,BOMMIM,CASRIM,1SECIM,2SE

CIM

yyyy 0100 0110

Y46

Elastic Store and

Excessive Zero

Interrupt Mask

#,#,#,#,#,#,#,#,#,#,#,EXZOIM,EXZIM,TXSLIPIM,

RXSLIPIM

yyyy 0100 0111

yyyy 0100 1111

Y47-Y4F

not used

xxxx indicates all (0000 to 1111) binary possibilities

X indicates all (0 to F) hex possibilities

yyyy indicates 9 (000, 001, 010, 011, 111,1000,1001) binary possibilities representing 1 of 8 framers (R/W), and

all 8 framers (W only) and global selection.

Y indicates 9 (0,1,2,3,4...9) hex possibilities representing 1 of 8 framers (R/W), and all 8 framers (W only) and

global selection.

Table 62 - Interrupt Mask Register (R/W) Address (Y4X) Summary (T1)

MT9072AB 数据表(PDF) 115 Page - Zarlink Semiconductor Inc

MT9072AB 数据表(HTML) 115 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载