MT9072AB datasheet(111/275 Pages) ZARLINK

111 / 275 page

MT9072

Data Sheet

111

Zarlink Semiconductor Inc.

yyyy 1111 0011

YF3

R/W HDLC Test Control

#,#,#,#,#,#,#,#,#,#.HRST,RTLOOP,CRCTST,FTST,

ADTST,HLOOP

yyyy 1111 0100

YF4

R/W Address Recognition

ADRM26-20,A2EN,ADRM16-10,AEN

yyyy 1111 0101

YF5

R/W TX FIFO

#,#,#,#,#,#,#,#,TXFIFO7-0

yyyy 1111 0110

YF6

R/W TX Byte count

#,#,#,#,#,#,#,#,CNT7-0

yyyy 1111 0111

YF7

R/W Transmit Set Delay

Bits 7 - 0.

#,#,#,#,#,#,#,#,TXSD7-0

yyyy 1111 1000

yyyy1111 1111

YF8-

YFF

not used

xxxx indicates all (0000 to 1111) binary possibilities

X indicates all (0 to F) hex possibilities

yyyy indicates 9 (000, 001, 010, 011, 111,1000,1001) binary possibilities representing 1 of 8 framers (R/W), all 8

framers (W only), and global selection.

Y indicates 9 (0,1,2,3,4...9) hex possibilities representing 1 of 8 framers (R/W), and all 8 framers (W only) and

global selection(R/W)

Binary

Address

(A11-A0)

Hex

Address R/W

Control Bits

(B15 - B8 / B7 - B0)

Table 58 - Master Control Registers Address (Y00 to Y0F and YF0 to YFF) Summary (T1)

MT9072AB 数据表(PDF) 111 Page - Zarlink Semiconductor Inc

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