CS89712 datasheet(110/170 Pages) CIRRUS

110 / 170 page

CS89712

110

DS502PP2

3.16.4

DAIDR1 DAI Data Register 1 (address 0x8000.2080)

When DAI Data Register 1 (DAIDR1) is read, the bottom entry of the Left Channel Receive FIFO is accessed. As

data is removed by the DAI’s receive logic from the incoming data frame, it is placed into the top entry of the Left

Channel Receive FIFO and is transferred down an entry at a time until it reaches the last empty location within the

FIFO. Data is removed by reading DAIDR1, which accesses the bottom entry of the left channel FIFO. After DAIDR1

is read, the bottom entry is invalidated, and all remaining values within the FIFO automatically transfer down one

location.

When DAIDR1 is written, the top-most entry of the Left Channel Transmit FIFO is accessed. After a write, data is

automatically transferred down to the lowest location within the transmit FIFO which does not already contain valid

data. Data is removed from the bottom of the FIFO one value at a time by the transmit logic. It is then loaded into

the correct position within the 64-bit transmit serial shifter then serially shifted out onto the SDOUT pin.

Table 60 shows DAIDR1. Note that the Transmit and Receive Left Channel FIFOs are cleared when the device is

reset, or by writing a zero to DAIEN (DAI disabled). Also, note that writes to reserved bits are ignored and reads

return zeros.

3.16.5

DAIDR2 DAI Data Register 2 (address 0x8000.20C0)

DAIDR2 is a 32-bit register that utilizes 21 bits and is used to enable and disable the FIFOs for the

left and right channels of the DAI data stream. The left channel FIFO is enabled by writing

0x000D.8000 and disabled by writing 0x000D.0000. The right channel FIFO is enabled by writing

0x0011.8000 and disabled by writing 0x0011.0000. After writing a value to this register, wait until the

16-31

Reserved

31-16

15-0

Reserved

Bottom of Left Channel Receive FIFO

Read Access

31-16

15-0

Reserved

Top of Left Channel Transmit FIFO

Write Access

Bit

Description

0-15

LEFT CHANNEL DATA: Transmit / Receive Left Channel FIFO Data

Read — Bottom of Left Channel Receive FIFO data

Write — Top of Left Channel Transmit FIFO data

16-31

Reserved

Table 60. DAI Data Register 1

31-21

20-16

14-0

Reserved

FIFO Channel Select

FIFOEN

Reserved

Bit

Description

Table 59. DAI Data Register 0 (Continued)

CS89712 数据表(PDF) 110 Page - Cirrus Logic

CS89712 数据表(HTML) 110 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS89712 数据表(PDF) 110 Page - Cirrus Logic

CS89712 数据表(HTML) 110 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载