CS89712 datasheet(111/170 Pages) CIRRUS

111 / 170 page

CS89712

DS502PP2

111

FIFO operation complete bit (FIFO) is set in the DAI status register before writing another value to this

3.16.6

DAISR DAI Status (address 0x8000.2100)

The DAI Status register (DAISR) contains bits which signal FIFO overrun and underrun errors and

FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller.

The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty,

when a FIFO operation is complete, and when the right channel or left channel portion of the CODEC

is enabled (no interrupt generated).

Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is

cleared, the interrupt is cleared. Read / write bits are called status bits, read-only bits are called flags.

Status bits are referred to as “sticky” (once set by hardware, they must be cleared by software). Writ-

ing a one to a sticky status bit clears it, while writing a zero has no effect. Read-only flags are set and

cleared by hardware, and writes have no effect. Additionally, some bits which cause interrupts have

corresponding mask bits in the control register and are indicated in the section headings below. Note

that the user has the ability to mask all DAI interrupts by clearing the DAI bit within the interrupt con-

troller mask register INTMR3.

Bit

Description

0-14

Reserved

FIFOEN: FIFO Transmit Bit

0 — Disable Transmit

1 — Enable Transmit

16-20

FIFO CHANNEL SELECT:

01101b — Left channel select

10001b — Right channel select

21-31

Reserved

Table 61. DAI Data Register 2

31-13

Reserved

FIFO

LCNE

LCNF

RCNE

RCNF

RCCELCRO

RCNFLCTU

LCRORCRO

LCTURCTU

LCRS

LCTS

LCRSRCRS

LCTSRCTS

Bit

Description

RCTS: Right Channel Transmit FIFO Service Request Flag (read-only)

0 — Right Channel Transmit FIFO is more than half full (five or more entries filled) or DAI dis-

abled

1 — Right Channel Transmit FIFO is half full or less (four or fewer entries filled) and DAI oper-

ation is enabled, interrupt request signaled if not masked

(if RCTM = 1)

Table 62.

DAI Control, Data and Status Register Locations

CS89712 数据表(PDF) 111 Page - Cirrus Logic

CS89712 数据表(HTML) 111 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS89712 数据表(PDF) 111 Page - Cirrus Logic

CS89712 数据表(HTML) 111 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载