CS89712 datasheet(114/170 Pages) CIRRUS

114 / 170 page

CS89712

114

DS502PP2

vice request and / or interrupt) is automatically cleared.

3.16.6.5

Right Channel Transmit FIFO Underrun Status (RCTU)

This is set when the Right Channel Transmit logic attempts to fetch data from the FIFO after it has

been emptied. When an underrun occurs, the Right Channel Transmit logic continuously transmits

the last valid right channel value which was transmitted before the underrun. Once data is placed in

the FIFO and it is transferred down to the bottom, the Right Channel Transmit logic uses the new val-

ue within the FIFO for transmission. When the RCTU bit is set, an interrupt request is made.

3.16.6.6

Right Channel Receive FIFO Overrun Status (RCRO)

This is set when the right channel receive logic attempts to place data into the Right Channel Receive

FIFO after it has been completely filled. Each time a new piece of data is received, the set signal to

the RCRO status bit is asserted, and the newly received data is discarded. This process is repeated

for each new sample received until at least one empty FIFO entry exists. When this bit is set, an in-

terrupt request is made.

3.16.6.7

Left Channel Transmit FIFO Underrun Status (LCTU)

The Left Channel Transmit FIFO Underrun Status Bit (LCTU) is set when the Left Channel Transmit logic at-

tempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the Left

Channel Transmit logic continuously transmits the last valid left channel value which was transmitted before

the underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the Left Channel

Transmit logic uses the new value within the FIFO for transmission. When the LCTU bit is set, an interrupt re-

quest is made.

3.16.6.8

Left Channel Receive FIFO Overrun Status (LCRO)

The Left Channel Receive FIFO Overrun Status Bit (LCRO) is set when the Left Channel Receive log-

ic places data into the Left Channel Receive FIFO after it has been completely filled. Each time a new

piece of data is received, the set signal to the LCRO status bit is asserted, and the newly received

sample is discarded. This process is repeated for each new piece of data received until at least one

empty FIFO entry exists. When the LCRO bit is set, an interrupt request is made.

3.16.6.9

Right Channel Transmit FIFO Not Full Flag (RCNF)

The Right Channel Transmit FIFO Not Full Flag (RCNF) is a read-only bit which is set whenever the

Right Channel Transmit FIFO contains one or more entries which do not contain valid data and is

cleared when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the

Right Channel Transmit FIFO. This bit does not request an interrupt.

3.16.6.10 Right Channel Receive FIFO Not Empty Flag (RCNE)

The Right Channel Receive FIFO Not Empty Flag (RCNELCNF) is a read-only bit which is set when

ever the Right Channel Receive FIFO contains one or more entries of valid data and is cleared when

it no longer contains any valid data. This bit can be polled when using programmed I/O to remove

remaining data from the receive FIFO. This bit does not request an interrupt.

3.16.6.11 Left Channel Transmit FIFO Not Full Flag (LCNF)

This is a read-only bit which is set when ever the Left Channel Transmit FIFO contains one or more

entries which do not contain valid data. It is cleared when the FIFO is full. This bit can be polled when

using programmed I/O to fill the Left Channel Transmit FIFO. This bit does not request an interrupt.

3.16.6.12 Left Channel Receive FIFO Not Empty Flag (LCNE)

This is a read-only bit set when the Left Channel Receive FIFO contains one or more entries of valid

CS89712 数据表(PDF) 114 Page - Cirrus Logic

CS89712 数据表(HTML) 114 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载