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CS89712 数据表(PDF) 117 Page - Cirrus Logic |
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CS89712 数据表(HTML) 117 Page - Cirrus Logic |
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117 / 170 page ![]() CS89712 DS502PP2 117 RxEvent, TxEvent, and BufEvent. The other two registers are counter-overflow reports: RxMISS and TxCOL. In ad- dition, ISQ is located at offset address 0008h. See Section 2.31, “Managing Interrupts & Status Queue”. Reset value is: 0000 0000 0000 0000 3.18.2 Receiver Configuration Register (RxCFG, address offset 102h) RxCFG determines what frame types will cause interrupts. After reset, if no EEPROM is found by the CS89712, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE- PROM”. Reset value is: 0000 0000 0000 0011 Bit Description 5:0 RegNum: The lower six bits describe which register (4, 8, C, 10 or 12) is contained in the ISQ. 7:6 F:8 RegContent: The upper ten bits contain the register data contents. Table 66. Interrupt Status Queue 76 5:0 F E D RSVD Skip_1 000011 ExtradataiE RuntiE CB A 9 8 CRCerroriE BufferCRC RSVD RSVD RxOKiE Bit Description 5:0 000011: These bits provide an internal address used by the CS89712 to identify this as register 3, the Receiver Configuration Register. 6 Skip_1: When set, this bit causes the last committed received frame to be deleted from the receive buffer. To skip another frame, this bit must be set again. This bit is not to be used if RxDMAonly (Bit 9) is set. Skip_1 is an Act-Once bit. See Section 2.32.4, “Buffering Held Receive Frames”. 8 RxOKiE: When set, there is an RxOK Interrupt if a frame is received without errors. RxOK interrupt is not generated when DMA mode is used for frame reception. A RSVD: Reserved - must be a “0” when writing to this register. B BufferCRC: When set, the received CRC is included with the data stored in the receive-frame buffer, and the four CRC bytes are included in the receive-frame length (Ethernet Port offset address 0402h). When clear, neither the receive buffer nor receive length include the CRC. C CRCerroriE: When set, there is a CRCerror Interrupt if a frame is received with a bad CRC. D RuntiE: When set, ther is a Runt Interrupt if a frame is received that is shorter than 64 bytes. The CS89712 always discards any frame that is shorter than 8 bytes. E ExtradataiE: When set, there is an Extradata Interrupt if a frame is received that is longer than 1518 bytes. The operation of this bit is independent of the received packet integrity (good or bad CRC). Table 67. Receiver Configuration |
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