CS89712 datasheet(120/170 Pages) CIRRUS

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CS89712

120

DS502PP2

3.18.5

Transmit Configuration Register (TxCFG, address offset 106h)

Each bit in TxCFG is an interrupt enable. When set, the interrupt is enabled as described below. When clear, there

is no interrupt.

After reset, if no EEPROM is found by the CS89712, then the register has the following initial state. If an EEPROM

is found, then the register’s initial value may be set by the EEPROM. See Section 2.24,

“Programming the EE-

PROM”.

Reset value is: 0000 0000 0000 0111

Note:

Bit 8 (TxOKiE) and Bit B (AnycolliE) are interrupts for normal transmit operation. Bits 6, 7, 9, A, and Fare

interrupts for abnormal transmit operation.

7:6

5:0

F:C

RSVD

000111

16colliE

AnycolliE

JabberiE

Out-of-window

TxOKiE

Bit

Description

5:0

000111: These bits provide an internal address used by the CS89712 to identify this as register

7, the Transmit Configuration Register.

TxOKiE: When set, an interrupt is generated if a packet is completely transmitted.

Out-of-windowiE: When set, an interrupt is generated if a late collision occurs (a late collision

is a collision which occurs after the first 512 bit times). When this occurs, the CS89712 forces a

bad CRC and terminates the transmission.

JabberiE: When set, an interrupt is generated if a transmission is longer than approximately 26

ms.

AnycolliE: When set, if one or more collisions occur during the transmission of a packet, an

interrupt occurs at the end of the transmission

F:C

16colliE: If the CS89712 encounters 16 normal collisions while attempting to transmit a partic-

ular packet, the CS89712 stops attempting to transmit that packet. When this bit is set, there is

an interrupt upon detecting the 16th collision.

7:6

RSVD: Reserved. must be a “0” when writing to this register.

Table 70. Transmit Configuration

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