CS89712 datasheet(124/170 Pages) CIRRUS

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CS89712

124

DS502PP2

3.18.9

Buffer Event Register (BufEvent, address offset 12Ch)

BufEvent gives the status of the transmit and receive buffers.

Reset value is: 0000 0000 0000 1100

Notes: With any event register, like BufEvent, all bits are cleared upon readout. The software is responsible for

processing all event bits.

5:0

RSVD

SWint

001100

RxDest

CBA

Rx128

RxMiss

TxUnder run

Rdy4Tx

Bit

Description

5:0

001100: These bits provide an internal address used by the CS89712 to identify this as register

C, the Buffer Event Register.

SWint: If set, there has been a software initiated interrupt. This bit is used in conjunction with

the SWint-X bit (Register B, BufCFG, Bit 6).

RSVD: Reserved; must be a “0” when writing to this register.

Rdy4Tx: If set, the CS89712 is ready to accept a frame from the software for transmission. If

Rdy4TxiE (Register B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 2.34,

“Transmit

Operation” for a description of the transmit bid process.)

TxUnderrun: This bit is set if CS89712 runs out of data before it reaches the end of the frame

(called a transmit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an

interrupt.

RxMiss: If set, one or more receive frames have been lost due to slow movement of data out of

the receive buffers. If RxMissiE (Register B, BufCFG, Bit A) is set, there is an interrupt.

Rx128: This bit is set after the first 128 bytes of an incoming frame have been received. This bit

will allow the software the option of preprocessing frame data before the entire frame is

received. If Rx128iE (Register B, BufCFG, Bit B) is set, there is an interrupt.

RxDest: When set, this bit shows that a receive frame has passed the Destination Address Fil-

ter criteria as defined in the RxCTL register (Register 5). This bit is useful as an early indication

of an incoming frame. It will be earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE

(Register B, BufCFG, Bit F) is set, there is an interrupt.

Table 74. Buffer Event

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