CS89712 datasheet(127/170 Pages) CIRRUS

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CS89712

DS502PP2

127

3.18.12 Line Control Register (LineCTL, address offset 112h)

LineCTL determines the configuration of the MAC engine and physical interface.

After reset, if no EEPROM is found by the CS89712, then the register has the following initial state. If an EEPROM

is found, then the register’s initial value may be set by the EEPROM. See Section 2.24,

“Programming the EE-

PROM”.

Reset value is: 0000 0000 0001 0011

5:0

SerTxOn

SerRxON

010011

LoRx Squelch

CBA

9:8

2-part DefDis

PolarityDis

Mod BackoffE

RSVD

Bit

Description

5:0

010011: These bits provide an internal address used by the CS89712 to identify this as register

13, the Line Control Register.

SerRxON: When set, the receiver is enabled. When clear, no incoming packets pass through

the receiver. If SerRxON is cleared while a packet is being received, reception is completed

and no subsequent receive packets are allowed until SerRxON is set again.

SerTxON: When set, the transmitter is enabled. When clear, no transmissions are allowed. If

SerTxON is cleared while a packet is being transmitted, transmission is completed and no sub-

sequent packets are transmitted until SerTxON is set again.

ModBackoffE: When clear, the ISO/IEC standard backoff algorithm is used (see Section 2.26,

“Media Access Control Engine”). When set, the Modified Backoff algorithm is used. (The Modi-

fied Backoff algorithm extends the backoff delay after each of the first three Tx collisions.)

PolarityDis: The 10BASE-T receiver automatically determines the polarity of the received sig-

nal at the RXD+/RXD- input (see Section 2.28,

“10BASE-T Transceiver”). When this bit is

clear, the polarity is corrected, if necessary. When set, no effort is made to correct the polarity.

This bit is independent of the PolarityOK bit (Register 14, LineST, Bit C), which reports whether

the polarity is normal or reversed.

2-partDefDis: Before a transmission can begin, the 89712 follows a deferral procedure. With

the 2-partDefDis bit clear, the CS89712 uses the standard two-part deferral as defined in

ISO/IEC 8802-3 paragraph 4.2.3.2.1. With the 2-partDefDis bit set, the two-part deferral is dis-

abled.

LoRxSquelch: When clear, the 10BASE-T receiver squelch thresholds are set to levels

defined by the ISO/IEC 8802-3 specification. When set, the thresholds are reduced by approx-

imately 6 dB. This is useful for operating with "quiet" cables that are longer than 100 meters.

9:8

RSVD: Reserved; must be a “0” when writing to this register.

Table 77. Line Control

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