 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
CS89712 数据表(PDF) 126 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS89712 数据表(HTML) 126 Page - Cirrus Logic |
|
|
126 / 170 page  CS89712 126 DS502PP2 3.18.11 Transmit Collision Counter (TxCOL, address offset 132h) The TxCOL counter (Bits 6 through F) is incremented whenever the 10BASE-T Receive Pair (RXD+ / RXD-) be- comes active while a packet is being transmitted. If the TxColOvfiE bit (Register B, BufCFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides the software with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over (by interrupting at 200h, the software has an additional 512 counts before TxCOL actually overflows). The TxCOL counter is cleared when read. Reset value is: 0000 0000 0001 0010 7:6 5:0 F:8 ColCount 010010 ColCount Bit Description 5:0 010010: These bits provide an internal address used by the CS89712 to identify this as register 12, the Transmit Collision Counter. When reading this register, these bits will be 010010, where the LSB corresponds to Bit 0. 7:6 F:8 ColCount: The upper ten bits contain the number of collisions. Table 76. Transmit Collision Counter |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
