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数据搜索系统，热门电子元器件搜索 |
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CS89712 数据表(PDF) 125 Page - Cirrus Logic |
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CS89712 数据表(HTML) 125 Page - Cirrus Logic |
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125 / 170 page  CS89712 DS502PP2 125 3.18.10 Receiver Miss Counter Register (RxMISS, address offset 130h) The RxMISS counter (Bits 6 through F) records the number of receive frames that are lost (missed) due to the lack of available buffer space. If the MissOvfloiE bit (Register B, BufCFG, Bit D) is set, there is an interrupt when RxMISS increments from 1FFh to 200h. This interrupt provides the software with an early warning that the RxMISS counter should be read before it reaches 3FFh and starts over (by interrupting at 200h, the software has an additional 512 counts before RxMISS actually overflows). The RxMISS counter is cleared when read. Register’s value is: 0000 0000 0001 0000 7:6 5:0 F:8 MissCount 010000 MissCount Bit Description 5:0 010000: These bits provide an internal address used by the CS89712 to identify this as register 10, the Receiver Miss Counter. When reading this register, these bits will be 010000, where the LSB corresponds to Bit 0. 7:6 F:8 MissCount: The upper ten bits contain the number of missed frames. Table 75. Receiver Miss Counter |
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