15

LM53602, LM53603

www.ti.com

SNVSAR0 – NOVEMBER 2016

Product Folder Links: LM53602 LM53603

Submit Documentation Feedback

Copyright © 2016, Texas Instruments Incorporated

Feature Description (continued)

Equation 2 can be used as a guide to indicate how the various terms affect the input supply current. The

Application Curves show measured values for the input supply current for both 3.3-V and 5-V output voltage

versions.

8.3.6 UVLO and TSD

The LM53603 incorporates an input undervoltage lockout (UVLO) function. The device accepts an EN command

when the input voltage rises above about 3.64 V and shuts down when the input falls below about 3.3 V. See the

Thermal shutdown is provided to protect the device from excessive temperature. When the junction temperature

reaches about 162°C, the device shuts down; restart occurs at a temperature of about 144ºC.

8.4 Device Functional Modes

See Table 1 and the following paragraphs for a detailed description of the functional modes for the LM53603.

These modes are controlled by the FPWM input as shown in Table 1. This input can be controlled by any

compatible logic, and the mode changed while the regulator is operating. If it is desired to lock the mode for a

given application, the input can be either connected to ground, a logic supply, or the VCC pin, as desired. The

maximum input voltage on this pin is 5.5 V and it should not be allowed to float.

Table 1. Mode Selection

FPWM INPUT VOLTAGE

OPERATING MODE

> 1.5 V

Forced PWM: The regulator operates as a constant frequency, current mode, full-

synchronous converter for all loads; without diode emulation.

< 0.4 V

AUTO: The regulator moves between PFM and PWM as the load current changes, using

diode-emulation-mode to allow DCM (see the Glossary).

8.4.1 AUTO Mode

In AUTO mode the device moves between PWM and PFM as the load changes. At light loads the regulator

operates in PFM. At higher loads the mode changes to PWM. The load currents for which the devices moves

from PWM to PFM can be found in the Application Curves.

In PWM , the converter operates as a constant frequency, current mode, full synchronous converter using PWM

to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a

constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line

and load regulation and low output voltage ripple. When in PWM, the converter synchronizes to any valid clock

signal on the SYNC input (see Dropout and Input Voltage Frequency Fold-Back).

In PFM the high-side FET is turned on in a burst of one or more cycles to provide energy to the load. The

frequency of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency.

This mode provides high light load efficiency by reducing the amount of input supply current required to regulate

the output voltage at small loads Glossary. This trades off very good light load efficiency for larger output voltage

ripple and variable switching frequency. Also, a small increase in the output voltage occurs in PFM. The actual

switching frequency and output voltage ripple depend on the input voltage, output voltage, and load. Typical

switching waveforms for PFM are shown in Figure 12. See the Application Curves for output voltage variation in

AUTO mode. The SYNC input is ignored during PFM operation.

A unique feature of this device, is that a minimum input voltage is required for the regulator to switch from PWM

to PFM at light load. This feature is a consequence of the advanced architecture employed to provide high

efficiency at light loads. Figure 13 indicates typical values of input voltage required to switch modes at no-load.

Also, once the regulator switches to PFM, at light load, it remains in that mode if the input voltage is reduced.