RESET

High = Power Good

Low = Fault

94%

93%

107%

106%

11

LM53602, LM53603

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SNVSAR0 – NOVEMBER 2016

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8.3 Feature Description

8.3.1 RESET Flag Output

The RESET function, built-in to the LM53603, has special features not found in the ordinary Power Good

function. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during line

and load transients. Furthermore, there is a delay between the point at which the output voltage is within

specified limits and the flag asserts Power Good. Because the RESET comparator and the regulation loop share

the same reference, the thresholds track with the output voltage. This allows the LM53603 to be specified with a

96.5% maximum threshold, while at the same time specifying a 95% threshold with respect to the actual output

voltage for that device. This allows tighter tolerance than is possible with an external supervisor device. The net

result is a more accurate power-good function while expanding the system allowance for transients, and so forth.

RESET operation can best be understood by reference to Figure 7 and Figure 8. The values for the various filter

and delay times can be found in the Timing Requirements table. Output voltage excursions lasting less than

imposed before RESET goes high.

This output consists of an open-drain NMOS; requiring an external pullup resistor to a suitable logic supply. It

needed, the pin should be left floating or grounded. When EN is pulled low, the flag output is also forced low.

With EN low, RESET remains valid as long as the input voltage is

≥ 1.5 V. The maximum current into this pin

should be limited to 1 mA, while the maximum voltage should be less than 8 V.

Figure 7. Static RESET Operation