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STM32L475VC 数据表(PDF) 52 Page - STMicroelectronics |
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STM32L475VC 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 193 page  Functional overview STM32L475xx 52/193 DocID027692 Rev 2 The Quad SPI interface supports: • Three functional modes: indirect, status-polling, and memory-mapped • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the 5 following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Programmable masking for external flash flag management • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error |
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