STM32L475VC datasheet(40/193 Pages) STMICROELECTRONICS

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Functional overview

STM32L475xx

40/193

DocID027692 Rev 2

3.21

Digital filter for Sigma-Delta Modulators (DFSDM)

The device embeds one DFSDM with 4 digital filters modules and 8 external input serial

channels (transceivers) or alternately 8 internal parallel inputs support.

The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to

microcontroller and then to perform digital filtering of the received data streams (which

represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse

Density Modulation) microphones and perform PDM to PCM conversion and filtering in

hardware. DFSDM features optional parallel data stream inputs from microcontrollers

memory (through DMA/CPU transfers into DFSDM).

DFSDM transceivers support several serial interface formats (to support various Σ∆

modulators). DFSDM digital filter modules perform digital processing according user

selected filter parameters with up to 24-bit final ADC resolution.

The DFSDM peripheral supports:

•

8 multiplexed input digital serial channels:

–

configurable SPI interface to connect various SD modulator(s)

–

configurable Manchester coded 1 wire interface support

–

PDM (Pulse Density Modulation) microphone input support

–

maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

–

clock output for SD modulator(s): 0..20 MHz

•

alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):

–

internal sources: device memory data streams (DMA)

•

4 digital filter modules with adjustable digital signal processing:

–Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)

–

integrator: oversampling ratio (1..256)

•

up to 24-bit output data resolution, signed output data format

•

automatic data offset correction (offset stored in register by user)

•

continuous or single conversion

•

start-of-conversion triggered by:

–

software trigger

–

internal timers

–

external events

–

start-of-conversion synchronously with first digital filter module (DFSDM0)

•

analog watchdog feature:

–

low value and high value data threshold registers

–

dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

–

input from final output data or from selected input digital serial channels

–

continuous monitoring independently from standard conversion

•

short circuit detector to detect saturated analog input values (bottom and top range):

–

up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream

–

monitoring continuously each input serial channel

•

break signal generation on analog watchdog event or on short circuit detector event

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