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STM32L475VC 数据表(PDF) 160 Page - STMicroelectronics |
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STM32L475VC 数据表(HTML) 160 Page - STMicroelectronics |
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160 / 193 page ![]() Electrical characteristics STM32L475xx 160/193 DocID027692 Rev 2 Table 79. TIMx(1) characteristics 1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time -1 - tTIMxCLK fTIMxCLK = 80 MHz 12.5 - ns fEXT Timer external clock frequency on CH1 to CH4 -0 fTIMxCLK/2 MHz fTIMxCLK = 80 MHz 0 40 MHz ResTIM Timer resolution TIMx (except TIM2 and TIM5) -16 bit TIM2 and TIM5 - 32 tCOUNTER 16-bit counter clock period - 1 65536 tTIMxCLK fTIMxCLK = 80 MHz 0.0125 819.2 µs tMAX_COUNT Maximum possible count with 32-bit counter - - 65536 × 65536 tTIMxCLK fTIMxCLK = 80 MHz - 53.68 s Table 80. IWDG min/max timeout period at 32 kHz (LSI)(1) 1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF Unit /4 0 0.125 512 ms /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 Table 81. WWDG min/max timeout value at 80 MHz (PCLK) Prescaler WDGTB Min timeout value Max timeout value Unit 1 0 0.0512 3.2768 ms 2 1 0.1024 6.5536 4 2 0.2048 13.1072 8 3 0.4096 26.2144 |
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