REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 42 –

Interrupt Mask Register (0Fh)

When an interrupt event occurs in the ADE7754, the IRQ logic output goes active low if the mask bit for this event is logic

one in this register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. The

following describes the function of each bit in the Interrupt Mask Register.

Table XVI MASK Register

Bit

Interrupt

Default

Location

Flag

Value

Description

0

AEHF

0

Enables an interrupt when there is a 0 to 1 transition of the MSB of the AENERGY register

(i.e. the AENERGY register is half-full)

1

SAGA

0

Enables an interrupt when there is a SAG on the line voltage of the Phase A

2

SAGB

0

Enables an interrupt when there is a SAG on the line voltage of the Phase B

3

SAGC

0

Enables an interrupt when there is a SAG on the line voltage of the Phase C

4

ZXTOA

0

Enables an interrupt when there is a zero crossing time out detection on Phase A

5

ZXTOB

0

Enables an interrupt when there is a zero crossing time out detection on Phase B

6

ZXTOC

0

Enables an interrupt when there is a zero crossing time out detection on Phase C

7

Z X A

0

Enables an interrupt when there is a rising zero crossing in voltage channel of the phase

A —Zero Crossing Detection

8

Z X B

0

Enables an interrupt when there is a rising zero crossing in voltage channel of the phase

B —Zero Crossing Detection

9

Z X C

0

Enables an interrupt when there is a rising zero crossing in voltage channel of the phase

C —Zero Crossing Detection

Ah

LENERGY

0

Enables an interrupt when the LAENERGY and LVAENERGY accumulations over

LINCYC are finished

B h

Reserved

C h

PKV

0

Enables an interrupt when the voltage input selected in the MMODE register is above the

value in the PKVLVL register

D h

PKI

0

Enables an interrupt when the current input selected in the MMODE register is above the

value in the PKILVL register.

E h

WFSM

0

Enables an interrupt when a data is present in the Waveform Register.

F h

VAEHF

0

Enables an interrupt when there is a 0 to 1 transition of the MSB of the VAENERGY

register (i.e. the VAENERGY register is half-full)

INTERRUPT MASK REGISTER*

ADDR: 0Fh

0

1

2

3

4

5

6

7

00

0

0

0

0

0

0

8

9

A

B

C

D

E

F

00

0

0

0

0

0

0

VAEHF

(Apparent Energy Register Half Full)

AEHF

(Active Energy Register Half Full)

SAG

(SAG Event Detect)

WFMP

(New Waveform Sample Ready)

*Register contents show power on defaults

ZX

(Zero Crossing Time out Detection)

PKV

LENERGY

(End of the LAENERGY and LVAENERGY accumulation)

ZX

(Zero Crossing Detection)

Reserved

PKI

(Current channel Peak detection)

(Voltage channel Peak detection)