ADE7754 datasheet(36/44 Pages) AD

36 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 36 –

Address

Default

[A5:A0]

Name

R/W*

Length

Value

Description

12h

ZXTOUT

R / W

FFFFh

Zero Cross Time Out register. If no zero crossing is detected

within a time period specified by this register the interrupt request

line (IRQ) will go active low for the corresponding line voltage.

The maximum time-out period is 2.3 seconds - see Zero Crossing

Detection.

13h

LINCYC

R/W

FFFFh

Line Cycle register. The content of this register sets the

number of half line cycles while the active energy and the appar-

ent energy are accumulated in the LAENERGY and

LVAENERGY registers - See Energy Calibration.

14h

SAGCYC

R/W

F F h

Sag Line Cycle register. This register specifies the number of

consecutive half-line cycles where voltage channel input falls be-

low a threshold level. This register is common to the three line

voltage SAG detection. The detection threshold is specified by

SAGLVL register - See Voltage SAG Detection.

15h

SAGLVL

R / W

SAG Voltage Level. This register specifies the detection threshold

for SAG event. This register is common to the three line voltage

SAG detection. See the description of SAGCYC register for de-

tails.

16h

VPEAK

R / W

F F h

Voltage Peak Level. This register sets the level of the voltage

peak detection. If the selected voltage phase exceeds this level, the

PKV flag in the status register is set - See Table XII.

17h

IPEAK

R / W

F F h

Current Peak Level. This register sets the level of the current

peak detection. If the selected current phase exceeds this level, the

PKI flag in the status register is set - See Table XII.

18h

GAIN

R / W

PGA Gain register. This register is used to adjust the gain selec-

tion for the PGA in current and voltage channels - See Analog

Inputs and Table X. This register is also used to configuration of

the active energy accumulation - No-load threshold and sum of

absolute values.

19h

A W G

R / W

Phase A Active Power Gain register. This register calculation can

be calibrated by writing to this register. The calibration range is

50% of the nominal full scale active power. The resolution of the

gain adjust is 0.0244% / LSB.

1Ah

B W G

R / W

Phase B Active Power Gain

1Bh

C W G

R / W

Phase C Active Power Gain

1Ch

AVAG

R / W

VA Gain register. This register calculation can be calibrated by

writing this register. The calibration range is 50% of the nominal

full scale real power. The resolution of the gain adjust is

0.02444% / LSB.

1Dh

BVAG

R / W

Phase B VA Gain

1Eh

CVAG

R / W

Phase C VA Gain

1Fh

APHCAL

R / W

Phase A Phase Calibration Register

20h

BPHCAL

R / W

Phase B Phase Calibration Register

21h

CPHCAL

R / W

Phase C Phase Calibration Register

22h

AAPOS

R / W

Phase A Power Offset Calibration Register

23h

BAPOS

R / W

Phase B Power Offset Calibration Register

24h

CAPOS

R / W

Phase C Power Offset Calibration Register

25h

CFNUM

R / W

CF Scaling Numerator register. The content of this register is

used in the numerator of CF output scaling.

26h

CFDEN

R / W

3Fh

CF Scaling Denominator register. The content of this register

is used in the denominator of CF output scaling.

27h

WDIV

R/W

Active Energy register divider

28h

VADIV

R / W

Apparent Energy register divider

29h

AIRMS

Phase A Current channel RMS register. The register contains the

RMS component of one input of the current channel. The source

is selected by data bits

in the mode register.

2Ah

BIRMS

Phase B Current channel RMS register.

2Bh

CIRMS

Phase C Current channel RMS register.

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ADE7754 数据表(PDF) 36 Page - Analog Devices

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