REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

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Operational Mode Register (0Ah)

The general configuration of the ADE7754 is defined by writing to the OPMODE register. Table IX below summarizes the

functionality of each bit in the OPMODE register .

Table IX OPMODE Register

Bit

Bit

Default

Location

Mnemonic

Value

Description

0

DISHPF

0

The HPF (High Pass Filter) in all current channel inputs are disabled when this bit is set.

1

DISLPF

0

The LPFs (Low Pass Filter) in all current channel inputs are disabled when this bit is set.

2

DISCF

1

The Frequency output CF is disabled when this bit is set.

3-5

DISMOD

0

By setting these bits, ADE7754’s A/D converters can be turned off. In normal operation,

these bits should be left at logic zero.

DISMOD2 DISMOD1 DISMOD0

0

0

0

Normal operation

1

0

0

Normal operation, by setting this bit to logic 1 the

analog inputs to current channel are connected to the ADC

for voltage channel and the analog inputs to voltage

channel are connected to the ADC for current channel

0

0

1

Current channel A/D converters OFF

1

0

1

Current channel A/D converters OFF + chan

nels swapped

0

1

0

Voltage Channel A/D converters OFF

1

1

0

Voltage Channel A/D converters OFF + chan

nels swapped

0

1

1

ADE7754 in Sleep Mode

1

1

1

ADE7754 powered down

6

SWRST

0

Software chip reset. A data transfer to the ADE7754 should not take place for at least 18µs

after a software reset.

7

RESERVED -

This is intended for factory testing only and should be left at zero.