ADE7754 datasheet(23/44 Pages) AD

23 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 23 –

Integration times under steady load

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 0.4µs (4/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

Watt Gain registers set to 000h, the average word value from

each LPF2 is D1B717h - see Figures 20 and 22. The

maximum value which can be stored in the Active Energy

23 -1 or 7F,FFFFh. As the

average word value is added to the internal register, which can

store 2

53 - 1 or 1F,FFFF,FFFF,FFFFh before it overflows,

the integration time under these conditions with WDIV=0 is

calculated as follows:

Time

F FFFF FFFF FFFFh

×=

1 717

,,,

When WDIV is set to a value different from 0, the integration

time varies as shown on Equation 10.

Time = TimeWDIV=0 x WDIV

(10)

The WDIV register can be used to increase the time before

the active energy register overflows, therefore reducing the

communication needs with the ADE7754.

Energy to Frequency Conversion

The ADE7754 also provides energy to frequency conversion

for calibration purposes. After initial calibration at manufac-

ture, the manufacturer or end customer will often verify the

energy meter calibration. One convenient way to verify the

meter calibration is for the manufacturer to provide an output

frequency which is proportional to the energy or active power

under steady load conditions. This output frequency can

provide a simple, single wire, optically isolated interface to

external calibration equipment. Figure 27 illustrates the

Energy to frequency conversion in the ADE7754.

CFNUM[11:0]

Active Power

Phase A

Active Power

Phase B

Active Power

Phase C

CFDEN[11:0]

DFC

53 Total Active

Power

Figure 27– ADE7754 Energy to Frequency Conversion

A Digital to Frequency Converter (DFC) is used to generate

the CF pulsed output. The DFC generates a pulse each time

one LSB in the Active Energy register is accumulated. An

output pulse is generated when CFDEN/CFNUM pulses are

generated at the DFC output. Under steady load conditions

the output frequency is proportional to the Active Power.

The

maximum

output

frequency

(CFNUM=00h

CFDEN=00h) with full scale AC signals on the three phases

i.e. current channel and voltage channel is approximately

96kHz.

The ADE7754 incorporates two registers to set the frequency

of CF (CFNUM[11:0] and CFDEN[11:0]). These are

unsigned 12-bit registers which can be used to adjust the

frequency of CF to a wide range of values. These Frequency

scaling registers are 12-bit registers which can scale the

output frequency by 1/2

12 to 1 with a step of 1/212.

If the value zero is written to any of these registers, the value

one would be applied to the register. The ratio CFNUM/

CFDEN should be smaller than one to assure proper opera-

tion. If the ratio of the registers CFNUM/CFDEN is greater

than one, the CF frequency can no longer be guaranteed to

be a consistent value.

For example if the output frequency is 18.744kHz while the

contents of CFDEN are zero (000h), then the output frequency

can be set to 6.103Hz by writing BFFh to the CFDEN

The output frequency will have a slight ripple at a frequency

equal to twice the line frequency. This is due to imperfect

filtering of the instantaneous power signal to generate the

Active Power signal – see ACTIVE POWER CALCULATION.

Equation 5 gives an expression for the instantaneous power

signal. This is filtered by LPF2 which has a magnitude

response given by Equation 11.

()

(11)

The Active Power signal (output of the LPF2) can be

rewritten as.

()

cos

=−

+ 

























⋅

()

(12)

where fl is the line frequency (e.g., 60Hz)

From Equation 8

VIt

( )

sin

=−

+ 

























⋅

()

(13)

From Equation 13 it can be seen that there is a small ripple

in the energy calculation due to a sin(2

ωt) component. This

is shown graphically in Figure 28. The ripple will get larger

as a percentage of the frequency at larger loads and higher

output frequencies. Choosing a lower output frequency at CF

for calibration can significantly reduce the ripple. Also

averaging the output frequency by using a longer gate time for

the counter will achieve the same results.

E(t)

VIt

(

sin

⋅





























−

Figure 28 – Output frequency ripple

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