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WM8281ECS/R 数据表(PDF) 135 Page - Cirrus Logic |
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WM8281ECS/R 数据表(HTML) 135 Page - Cirrus Logic |
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135 / 392 page ![]() WM8281 Rev 4.0 135 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 DSP3_WDMA_A CTIVE_CHANNE LS [7:0] 00h DSP3 WDMA Channel Status There are 8 WDMA channels; each bit of this field indicates the status of the respective WDMA channel. Each bit is coded as: 0 = Inactive 1 = Active R4880 (1310h) to R4887 (1317h) 15:0 DSP3_START_A DDRESS_WDMA _BUFFER_n [15:0] 0000h DSP3 WDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP3_WDMA_CHANNEL_OFFSET bit. R4896 (1320h) to R4901 (1325h) 15:0 DSP3_START_A DDRESS_RDMA _BUFFER_n [15:0] 0000h DSP3 RDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP3_RDMA_CHANNEL_OFFSET bit. R4912 (1330h) DSP3 WDMA Config 1 13:0 DSP3_WDMA_B UFFER_LENGTH [13:0] 0000h DSP3 DMA Buffer Length Selects the amount of data transferred in each WDMA channel. The LSB represents one 24-bit DSP memory word. R4913 (1331h) DSP3 WDMA Config 2 7:0 DSP3_WDMA_C HANNEL_ENABL E [7:0] 00h DSP3 WDMA Channel Enable There are 8 WDMA channels; each bit of this field enables the respective WDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R4914 (1332h) DSP3 WDMA Offset 1 7:0 DSP3_WDMA_C HANNEL_OFFSE T [7:0] 00h DSP3 WDMA Channel Offset There are 8 WDMA channels; each bit of this field offsets the Start Address of the respective WDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h |
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