WM8281ECSSLASHR datasheet(32/392 Pages) CIRRUS

32 / 392 page

WM8281

Rev 4.0

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal Clocking

SYSCLK frequency

SYSCLK_FREQ=000, SYSCLK_FRAC=0

-1%

6.144

+1%

MHz

SYSCLK_FREQ=000, SYSCLK_FRAC=1

-1%

5.6448

+1%

SYSCLK_FREQ=001, SYSCLK_FRAC=0

-1%

12.288

+1%

SYSCLK_FREQ=001, SYSCLK_FRAC=1

-1%

11.2896

+1%

SYSCLK_FREQ=010, SYSCLK_FRAC=0

-1%

24.576

+1%

SYSCLK_FREQ=010, SYSCLK_FRAC=1

-1%

22.5792

+1%

SYSCLK_FREQ=011, SYSCLK_FRAC=0

-1%

49.152

+1%

SYSCLK_FREQ=011, SYSCLK_FRAC=1

-1%

45.1584

+1%

SYSCLK_FREQ=100, SYSCLK_FRAC=0

-1%

73.728

+1%

SYSCLK_FREQ=100, SYSCLK_FRAC=1

-1%

67.7376

+1%

SYSCLK_FREQ=101, SYSCLK_FRAC=0

-1%

98.304

+1%

SYSCLK_FREQ=101, SYSCLK_FRAC=1

-1%

90.3168

+1%

SYSCLK_FREQ=110, SYSCLK_FRAC=0

-1%

147.456

+1%

SYSCLK_FREQ=110, SYSCLK_FRAC=1

-1%

135.4752

+1%

ASYNCCLK frequency

ASYNC_CLK_FREQ=000

-1%

6.144

+1%

MHz

-1%

5.6448

+1%

ASYNC_CLK_FREQ=001

-1%

12.288

+1%

-1%

11.2896

+1%

ASYNC_CLK_FREQ=010

-1%

24.576

+1%

-1%

22.5792

+1%

ASYNC_CLK_FREQ=011

-1%

49.152

+1%

-1%

45.1584

+1%

Note:

When MCLK1 or MCLK2 is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency

must be within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting.

WM8281ECS/R 数据表(PDF) 32 Page - Cirrus Logic

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