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WM8281ECS/R 数据表(PDF) 38 Page - Cirrus Logic

部件名 WM8281ECS/R
功能描述  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8281ECS/R 数据表(HTML) 38 Page - Cirrus Logic

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WM8281
38
Rev 4.0
CONTROL INTERFACE TIMING
2-WIRE (I2C) CONTROL MODE
SCLK
(input)
SDA
t4
t3
START
t8
STOP
t2
t1
t7
t6
t5
t9
t10
Figure 8 Control Interface Timing - 2-wire (I2C) Control Mode
Test Conditions
The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
SCLK Frequency
3400
kHz
SCLK Low Pulse-Width
t1
160
ns
SCLK High Pulse-Width
t2
100
ns
Hold Time (Start Condition)
t3
160
ns
Setup Time (Start Condition)
t4
160
ns
SDA, SCLK Rise Time
(10% to 90%)
SCLK frequency > 1.7MHz
t6
80
ns
SCLK frequency > 1MHz
160
SCLK frequency
≤ 1MHz
2000
SDA, SCLK Fall Time
(90% to 10%)
SCLK frequency > 1.7MHz
t7
60
ns
SCLK frequency > 1MHz
160
SCLK frequency
≤ 1MHz
200
Setup Time (Stop Condition)
t8
160
ns
SDA Setup Time (data input)
t5
40
ns
SDA Hold Time (data input)
t9
0
ns
SDA Valid Time
(data/ACK output)
SCLK slew (90% to 10%) = 20ns,
CLOAD (SDA) = 15pF
t10
40
ns
SCLK slew (90% to 10%) = 60ns,
CLOAD (SDA) = 100pF
130
SCLK slew (90% to 10%) = 160ns,
CLOAD (SDA) = 400pF
190
SCLK slew (90% to 10%) = 200ns,
CLOAD (SDA) = 550pF
220
Pulse width of spikes that will be suppressed
tps
0
25
ns



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