 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
WM8281ECS/R 数据表(PDF) 39 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8281ECS/R 数据表(HTML) 39 Page - Cirrus Logic |
|
|
39 / 392 page  WM8281 Rev 4.0 39 4-WIRE (SPI) CONTROL MODE SS (input) SCLK (input) MOSI (input) tSSU tSCH tSCL tSCY tDHO tDSU tSHO Figure 9 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle) SCLK (input) MISO (output) tDL SS (input) Figure 10 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle) Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT SS ¯¯ falling edge to SCLK rising edge tSSU 2.6 ns SCLK falling edge to SS ¯¯ rising edge tSHO 0 ns SCLK pulse cycle time SYSCLK disabled (SYSCLK_ENA=0) tSCY 38.4 ns SYSCLK_ENA=1 and SYSCLK_FREQ = 000 76.8 SYSCLK_ENA=1 and SYSCLK_FREQ > 000 38.4 SCLK pulse width low tSCL 15.3 ns SCLK pulse width high tSCH 15.3 ns MOSI to SCLK set-up time tDSU 1.5 ns MOSI to SCLK hold time tDHO 1.7 ns SCLK falling edge to MISO transition SCLK slew (90% to 10%) = 5ns, CLOAD (MISO) = 25pF tDL 0 11.9 ns |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
