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WM8281ECS/R 数据表(PDF) 41 Page - Cirrus Logic |
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WM8281ECS/R 数据表(HTML) 41 Page - Cirrus Logic |
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41 / 392 page ![]() WM8281 Rev 4.0 41 Test Conditions The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL MIN TYP MAX UNIT SLIMDAT Output SLIMDAT time for data output valid (wrt SLIMCLK rising edge) CLOAD = 15pF, SLIMDAT_DRV_STR=0, DBVDD1=1.62V TDV 4.7 8.1 ns CLOAD = 15pF, SLIMDAT_DRV_STR=1, DBVDD1=1.62V 4.3 7.3 CLOAD = 30pF, SLIMDAT_DRV_STR=0, DBVDD1=1.62V 6.8 11.8 CLOAD = 30pF, SLIMDAT_DRV_STR=1, DBVDD1=1.62V 5.8 10.0 CLOAD = 50pF, SLIMDAT_DRV_STR=0, DBVDD1=1.62V 9.6 16.6 CLOAD = 50pF, SLIMDAT_DRV_STR=1, DBVDD1=1.62V 7.9 13.7 CLOAD = 70pF, SLIMDAT_DRV_STR=0, DBVDD1=1.62V 12.4 21.5 CLOAD = 70pF, SLIMDAT_DRV_STR=1, DBVDD1=1.62V 10.0 17.4 SLIMDAT slew rate (20% to 80%) CLOAD = 15pF, SLIMDAT_DRV_STR=0 SRDATA 0.64 x VDBVDD1 V/ns CLOAD = 30pF, SLIMDAT_DRV_STR=0 0.35 x VDBVDD1 CLOAD = 30pF, SLIMDAT_DRV_STR=1 0.46 x VDBVDD1 CLOAD = 70pF, SLIMDAT_DRV_STR=0 0.16 x VDBVDD1 CLOAD = 70pF, SLIMCLK_DRV_STR=1 0.21 x VDBVDD1 Other Parameters Driver disable time TDD 6 ns Bus holder output impedance 0.1 x VDBVDD1 < V < 0.9 x VDBVDD1 RDATAS 18 50 k Ω |
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