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WM8281ECS/R 数据表(PDF) 205 Page - Cirrus Logic |
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WM8281ECS/R 数据表(HTML) 205 Page - Cirrus Logic |
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205 / 392 page ![]() WM8281 Rev 4.0 205 REGISTER ADDRESS BIT LABEL DEFAUL T DESCRIPTION R723 (02D3h) Jack detect analogue 0 JD1_ENA 0 JACKDET enable 0 = Disabled 1 = Enabled R3413 (0D55h) AOD IRQ Raw Status 0 JD1_STS 0 JACKDET input status 0 = Jack not detected 1 = Jack is detected (Assumes the JACKDET pin is pulled ‘low’ on Jack insertion.) R3414 (0D56h) Jack detect debounce 0 JD1_DB 0 JACKDET input de-bounce 0 = Disabled 1 = Enabled Table 75 Jack Detect Control A recommended connection circuit, including headphone output on HPOUT1 and microphone connections, is shown in Figure 61. See “Applications Information” for details of recommended external components. WM8281 HPOUT1L HPOUT1R HPOUT1FB1 JACKDET MICDET1 Note: The illustrated circuit assumes the jack insertion switch contacts are closed when jack is inserted. * Note that the Right analogue mic channel is recommended with the external accessory detect function (jack insertion switch) MICBIASn 2.2k (+/-2%) C * INnRP Figure 61 Jack Detect and External Accessory Connections The internal comparator circuit used to detect the JACKDET status is illustrated in Figure 62. The threshold voltages for the jack detect circuit are noted in the “Electrical Characteristics”. Note that separate thresholds are defined for jack insertion and jack removal. JACKDET + - reference AVDD Jack Detect logic 1M (jack insertion switch) Note: The illustrated circuit assumes the jack insertion switch contacts are closed when jack is inserted. Figure 62 Jack Detect Comparator |
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