WM8281ECSSLASHR datasheet(312/392 Pages) CIRRUS

312 / 392 page

WM8281

312

Rev 4.0

JTAG INTERFACE

The JTAG interface provides test and debug access to the WM8281 DSP core. The interface

comprises 5 pins, as detailed below.



TCK: Clock input



TDI: Data input



TDO: Data output



TMS: Mode select input



TRST: Test Access Port reset input (active low)

For normal operation (test and debug access disabled), the JTAG interface should be held in reset (ie.

TRST should be at logic 0). An internal pull-down resistor holds the TRST pin low when not actively

driven.

The other JTAG input pins (TCK, TDI, TMS) should also be held at logic 0 for normal operation. An

internal pull-down resistor holds these pins low when not actively driven.

If the JTAG interface is enabled (TRST de-asserted, and TCK active) at the time of Power-On Reset,

or any other Reset, then a Software Reset must be scheduled, with the TCK input stopped or TRST

asserted (logic ‘0’), before using the JTAG interface.

As a general rule, it is recommended to always schedule a Software Reset before starting the JTAG

clock, or de-asserting the JTAG reset. In this event, the JTAG interface should be held in its reset

state until the Software Reset has completed, and the BOOT_DONE_STS bit has been set.

See “Hardware Reset, Software Reset, Wake-Up, and Device ID” for further details of the WM8281

Software Reset.

WM8281ECS/R 数据表(PDF) 312 Page - Cirrus Logic