P83C266BDR datasheet(5/92 Pages) PHILIPS

5 / 92 page

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MGL302

8-bit internal bus

8-BIT

WATCHDOG

TIMER

(T3)

ROM

32 KBYTES(1)

EPROM

64 KBYTES(2)

RAM

512 BYTES(1)

2 KBYTES(2)

× 7-BIT

DACS

× 4-BIT

ADCS

14-BIT DAC

ON SCREEN DISPLAY

(OSD)

PLL

internal

interrupts

external

interrupts

PWM0 to PWM7(4)

VPP

RESET

I2C-BUS

INTERFACE

ADC1(5)

ADC2(5)

ADC0(5)

SDA(3) SCL(3)

TWO 16-BIT

TIMER/

COUNTERS

(T0 AND T1)

T0(3)

T1(3)

VSSD

VDDD

FUNCTION

COMBINED

PARALLEL

I/O PORTS

PARALLEL

I/O PORT

CPU

80C51 CORE

EXCLUDING

ROM/RAM

XTALIN

XTALOUT

TPWM(4)

HSYNC

P8xCx66

VSYNC

VDDA

VSSA

Fig.1 P83C366 and P87C766 block diagram.

(1) For the P83C366.

(2) For the P87C766.

(3) Alternative functions of Port 1.

(4) Alternative functions of Port 5, except PWM7 which is an alternative function of Port 3.

(5) Alternative functions of Port 3.

P83C266BDR 数据表(PDF) 5 Page - NXP Semiconductors

P83C266BDR 数据表(HTML) 5 Page - NXP Semiconductors

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