P83C266BDR datasheet(29/92 Pages) PHILIPS

29 / 92 page

1999 Mar 10

Philips Semiconductors

Product speciﬁcation

Microcontrollers for PAL/SECAM TV

with OSD and VST

P8xCx66 family

11.10 VSYNC interrupt and level status bit

The SFR VINT is read-only. Figure 13 shows the timing diagram of VSYNC interrupt.

Table 33 VSYNC Interrupt Register (SFR address C9H)

Table 34 Description of VINT bits

11.10.1 EXTERNAL INTERRUPT REQUEST (IQ7)

A rising or falling edge (see Fig.13) of the active VSYNC signal generates a pending interrupt to the CPU and drives IQ7

HIGH (IQ7 resides in the SFR IRQ1). In the service routine, this bit should be cleared before return to main routine.

As long as this bit is HIGH a pending interrupt is always there. Each time VSYNC is activated by a rising or falling edge,

IQ7 is set HIGH. If the interrupt is not serviced before the next leading VSYNC edge, then IQ7 is written HIGH again and

no error of overrun is indicated.

76543210

−−−−−−−

VLVL

BIT

SYMBOL

DESCRIPTION

7to1

−

These 7 bits are not used.

VLVL

VSYNC input pin level. The state of this bit indicates the level of the VSYNC input. As

the input polarity of VSYNC is programmable two situations may be deﬁned.

If VSYNC is programmed active HIGH then:

VLVL = 0, means VSYNC is at a LOW level, i.e. raster scan period

VLVL = 1, means VSYNC is at HIGH level, i.e.vertical ﬂy-back period.

If VSYNC is programmed to active LOW then:

VLVL = 0, means VSYNC is at LOW level, i.e. vertical ﬂy-back period

VLVL = 1, means VSYNC is at HIGH level, i.e. raster scan period

Fig.13 Timing diagram of VSYNC interrupt.

handbook, full pagewidth

VSYNC

VSYNC active LOW (Vp = 0)

VSYNC active HIGH (Vp = 1)

MGL286

The falling edge of VSYNC generates interrupt

The rising edge of VSYNC generates an interrupt

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