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P83C266BDR 数据表(PDF) 81 Page - NXP Semiconductors

部件名 P83C266BDR
功能描述  80C51 8-bit CPU
PDF  92 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

P83C266BDR 数据表(HTML) 81 Page - NXP Semiconductors

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22 PINNING CHARACTERIZATION
This chapter describes every pin used in both the SDIP42 and PLCC68 packages.
22.1
Type of packages
SDIP42: for P8XCX66
PLCC68: for Metalink+ applications
Table 91 Explanation of symbols/terms used in Table 92
Table 92 Pin characteristics
SYMBOL/TERM
MEANING
STr
Schmitt trigger
Rpu
pull-up resistor
Rpd
pull-down resistor
Z
high-impedance
original state
the outputs keep the state they had before entering the Idle mode
PIN
SYMBOL
TYPE
INPUT LEVEL
OUTPUT TYPE
SLOPE
CONTROL
OUTPUT IN
IDLE MODE
OUTPUT
AFTER RESET
ACTIVE STATE
SW CONTROL
SDIP42
PLCC68
−
1VSS
−−
−
−
−
−
−
2
INTD
I
CMOS + Rpu(1)
−−
−
−
1
3
P5.0
I/O
CMOS
open-drain
Yes
original state
Z(2)
1
3
TPWM
O
−
push-pull
No
LOW
−
2
4
P5.1
I/O
CMOS
open-drain
Yes
original state
Z(2)
2
4
PWM0
O
−
open-drain
Yes
LOW
−
3
5
P5.2
I/O
CMOS
open-drain
Yes
original state
Z(2)
3
5
PWM1
O
−
open-drain
Yes
LOW
−
4
6
P5.3
I/O
CMOS
open-drain
Yes
original state
Z(2)
4
6
PWM2
O
−
open-drain
Yes
LOW
−
5
7
P5.4
I/O
CMOS
open-drain
Yes
original state
Z(2)
5
7
PWM3
O
−
open-drain
Yes
LOW
−
6
8
P5.5
I/O
CMOS
open-drain
Yes
original state
Z(2)
6
8
PWM4
O
−
open-drain
Yes
LOW
−
−
9
n.c.
−−
−
−
−
−



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