P83C266BDR datasheet(80/92 Pages) PHILIPS

80 / 92 page

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MGM676

tOZ

High Z

tACC(OE)

VDDP

(power supply)

D0 to D7

A0 to Axx

address

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tW(P)

th(WE)

th(A)

tsu(A)

th(D)

tsu(D)

tsu(PV)

tsu(OE)

tW(OE)

VPP

(program voltage)

data out

VIH

VIL

address valid

programming

verify

data invalid

data out

Fig.48 Programming waveforms.

VIH and VIL are CMOS levels and are typically 5 V and 0 V respectively.

When OE is HIGH, P0.0 to P0.7 are used as inputs, when OE is LOW, P0.0 to P0.7 are used as outputs.

During programming the power supply must remain at 5 V. During verification the power supply must remain at 5.8 V.

P83C266BDR 数据表(PDF) 80 Page - NXP Semiconductors

P83C266BDR 数据表(HTML) 80 Page - NXP Semiconductors

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