ADP5090ACPZ-1-R7 datasheet(15/22 Pages) AD

15 / 22 page

ADP5090

Data Sheet

Rev. C | Page 14 of 21

The equivalent resistor of the three external configuration

resistor dividers, RE, is equivalent to the paralleling value of the

three resistor dividers.

POWER GOOD (PGOOD)

The ADP5090 allows users to set a programmable PGOOD

voltage (VPGOOD) threshold, which indicates the SYS voltage is at

an acceptable level. It must be set using external resistors. Figure 30

shows the VPGOOD falling threshold voltage given by Equation 5.













REF

PGOOD

SYS

(5)

The ADP5090 has an internal resistor to program the hysteresis,

RSYS_PG_HYS = 103.5 kΩ (typical), given by Equation 6.

HYS

SYS

PGOOD

SYS

HYS

PGOOD

SYS

(6)

where VSYS_PGOOD_HYS is the PGOOD hysteresis voltage.

The equivalent resistor of the three external configuration

resistor dividers, RE, is recommended to be comprised of the

same three resistor dividers for easy resistor selection. Considering

the quiescent current consumption, the sum of the resistors that

comprise the power good resistor divider (RSYS_PG_HYS, RPG1, and

RPG2) must be more than 6 MΩ, that is,

RSYS_PG_HYS + RPG1 + RPG2 ≥ 6 MΩ

(7)

The logic high level on PGOOD is equal to the SYS voltage and

the logic low level is ground. The logic high level has approximately

11.8 kΩ (typical) internally in series to limit the available current.

The VPGOOD threshold must be greater than or equal to the VBAT_SD

threshold.

For the best operation of the system, set up PGOOD to drive an

external PFET between SYS and the system load via an inverter

in order to determine when the load can be connected or removed

to optimize the storage element capacity (see Figure 36). It is

necessary to complete the cold start-up if the system load

cannot be disabled.

Table 5 shows programming threshold resistor examples

corresponding to various voltages with a 10 MΩ resistor divider.

Figure 31 shows states of various threshold voltages.

Figure 31. States of Various Threshold Voltages

Table 5. Programming Threshold Resistors

Voltage Threshold (V)

RSD1 and RPG1 (MΩ)

RSD2 and RPG2 (MΩ)

RTERM1 (MΩ)

RTERM2 (MΩ)

3.92

6.04

Not applicable

2.1

4.22

5.76

Not applicable

2.2

4.53

5.49

1.74

8.25

2.3

4.75

5.23

2.1

7.87

2.4

4.99

2.43

7.5

2.5

5.11

4.87

2.74

7.32

2.6

5.36

4.64

3.01

6.98

2.7

5.49

4.53

3.3

6.65

2.8

5.62

4.32

3.48

6.49

2.9

5.76

4.22

3.74

6.2

5.9

4.02

3.92

6.04

3.1

6.04

3.9

4.12

5.9

3.2

6.2

3.74

4.32

5.62

3.3

6.34

3.65

4.53

5.49

3.4

6.49

3.57

4.64

5.36

3.5

6.49

3.48

4.87

5.23

3.6

6.65

3.4

4.99

3.7

6.8

3.3

5.1

4.87

3.8

6.81

3.2

5.23

4.75

3.9

6.98

3.09

5.36

4.64

COLD-STARTUP

MAIN BOOST

CHARGER ON

ENABLE CHIP

VSYS_TH

TURN ON MAIN BOOST IN

ASYNCHRONOUS MODE

VBAT_SD

VBAT_SD_HYS

MAIN BOOST IN

SYNCHRONOUS MODE

TURN ON SWITCH BETWEEN

BSTO AND BAT

VBAT_PG

VBAT_PG_HYS

PGOOD BECOMES HIGH

VBAT_TERM_HYS

VBAT_TERM

MAIN BOOST

CHARGER OFF

MAXIMUM DEVICE

RATING VOLTAGE

TURN OFF MAIN BOOST

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