ADP5090

Data Sheet

Rev. C | Page 16 of 21

APPLICATIONS INFORMATION

The ADP5090 extracts the energy from the VIN pin to charge

the SYS and BAT pins. This occurs in three stages: cold start,

asynchronous boost, and synchronous boost. This section

describes the procedures for selecting the external components

to maintain the energy transmission system with the layout and

assembly consideration.

ENERGY HARVESTER SELECTION

The energy harvester input source must provide a minimum level

of power for cold start, asynchronous boost, and synchronous

boost. The minimum input power required to complete cold

start can be estimated using the following equation:

where:

cold start real input power.

worst case.

the system load accelerates the cold start. Programming the

PGOOD threshold to enable the system load current is

recommended.

After the ADP5090 completes the cold start, the MPPT

function enables. To meet the average system load current, the

input source must provide the boost regulator with enough

power to charge the storage element fully while the system is in

low power or sleep mode. The power required by the system

can be estimated using the following equation:

where:

in the Typical Performance Characteristics section for more

information.

of worst case.

ENERGY STORAGE ELEMENT SELECTION

In order to protect the storage element from overcharging or

overdischarging, the storage element must be connected to the

BAT pin and the system load tied to the SYS pin. The ADP5090

supports many types of storage elements, such as rechargeable

batteries, super capacitors, and conventional capacitors. A

storage element with a 100 μF equivalent capacitance is required to

filter the pulse currents of the PFM switching converter. The

storage element capacity must provide the entire system load

when the input source is no longer generating power.

If there is high pulse current or the storage element has significant

impedance, it may be necessary to increase the SYS capacitor

from the 4.7 μF minimum, or add additional capacitance to the

BAT pin in order to prevent a droop in the SYS voltage. Note

that increasing the SYS capacitor causes the boost regulator to

operate in the less efficient cold start stage for a longer period at

startup. If the application cannot accept the longer cold start

time, place the additional capacitor parallel to the storage element.

See the Capacitor Selection section for more information.

INDUCTOR SELECTION

The boost regulator needs an appropriate inductor for proper

operation. The inductor saturation current must be at least 30%

higher than the expected peak inductor currents, as well as a

low series resistance (DCR) to maintain high efficiency. The

boost regulator internal control circuitry is designed to optimize

the efficiency and control the switching behavior with a nominal

inductance of 22 μH ± 20%. Table 7 lists some recommended

inductors.

Table 7. Recommended Inductors

Vendor

Device No.

L

(µH)

ISAT

(A)

IRMS

(A)

DCR

(mΩ)

Würth

Elektronik

74437324220

22

2

1

470

744042220

22

0.6

0.88

255

Coilcraft

LPS4018-223M

22

0.8

0.65

360

CAPACITOR SELECTION

Low leakage capacitors are required for ultralow power

applications that are sensitive to the leakage current. Any

leakage from the capacitors reduces efficiency, increases the

quiescent current, and degrades the MPPT effectiveness.

Input Capacitor

stores energy from the input source. For the energy harvester,

the source impedance is dominated by capacitive behavior.

Scale the input capacitor according to the value of the output

capacitance of the energy harvester; a minimum of 4.7 μF is

recommended.

For the primary battery as an input source application, a larger

capacitance helps to reduce the input voltage ripple and keep

the source current stable in order to extend the battery life.

SYS Capacitor

The ADP5090 requires two capacitors to be connected between

the SYS pin and the PGND pin. Connect a low ESR ceramic

capacitor of at least 4.7 μF parallel to a high frequency bypass

capacitor of 0.1 μF. Connect the bypass capacitor as close as

possible between SYS and PGND.