WM9713 datasheet(83/111 Pages) WOLFSON

83 / 111 page

Preliminary Technical Data

WM9713L

PTD, March 2004, Rev 2.2

LOW POWER STANDBY MODE

If all the bits in registers 26h, 3Ch and 3Eh are set except VMID1M (register 3Ch, bit 14), then the

WM9713L is in low-power standby mode and consumes very little current. A 1M

Ω resistor string

remains connected across AVDD to generate VREF. This is necessary if the on-chip analogue

comparators are used (see “Battery Alarm and Battery Measurement” section), and helps shorten the

delay between wake-up and playback readiness. If VREF is not required, the 1M

Ω resistor string can

be disabled by setting the VMID1M bit, reducing current consumption further.

SAVING POWER AT LOW SUPPLY VOLTAGES

The analogue supplies to the WM9713L can run from 1.8V to 3.6V. By default, all analogue circuitry

on the IC is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to

1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents

used in the analogue circuitry. This is controlled as shown below.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

5Ch

6:5

VBIAS

Analogue Bias optimization

11 : Lowest bias current, optimized for 1.8V

10 : Low bias current, optimized for 2.5V

01, 00 : Default bias current, optimized for 3.3V

Table 66 Analogue Bias Selection

POWER ON RESET (POR)

The WM9713L has an internal power on reset (PORB) which ensures that a reset is applied to all

registers until a supply threshold has been exceeded. The POR circuitry monitors the voltage for both

AVDD and DCVDD and will release the internal reset signal once these supplies are both nominally

greater than 1.36V. The internal reset signal is an AND of the PORB and RESETB input signal.

It is recommended that for operation of the WM9713L, all device power rails should be stable before

configuring the device for operation.

AC97 INTERFACE TIMING

Test Characteristics:

DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25

°C to +85°C, unless otherwise

stated.

CLOCK SPECIFICATIONS

BITCLK

SYNC

CLK_HIGH

CLK_LOW

CLK_PERIOD

SYNC_HIGH

SYNC_LOW

SYNC_PERIOD

Figure 28 Clock Specifications (50pF External Load)

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