WM9713 datasheet(21/111 Pages) WOLFSON

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Preliminary Technical Data

WM9713L

PTD, March 2004, Rev 2.2

INTEGER N MODE

The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz which is divided by 4 to achieve

a nominal system clock of 24.576MHz.

The integer division ratio (N) is determined by: FPLL_out / FPLL_IN , and is set by N[3:0] and must be in

the range 5 to 12 for integer N operation (0101 = div by 5, 1100 = div by 12). Note that setting LF=1

enables a further division by 4 required for input frequencies in the range 2.048MHz – 4.096MHz.

Integer N mode is selected by setting SDM=0.

FRACTIONAL N MODE

Fractional N mode provides a divide resolution of 1/2

22 and is set by K[21:0] (register 46h, see

section PLL Register Page Address Mapping). The relationship between the required division X, the

fractional division K[21:0] and the integer division N[3:0] is:

()

−

= 22

where 0 < (X – N) < 1 and K is rounded to the nearest whole number.

For example, if the PLL_IN clock is 13MHz and the desired PLL_OUT clock is 98.304MHz then the

desired division, X, is 7.5618. So N[3:0] will be 7h and K[21:0] will be 23F488h to produce the desired

98.304MHz clock (see Table 4).

INPUT CLOCK (PLL_IN)

DESIRED

PLL

OUTPUT

(PLL_OUT)

DIVISION

REQUIRED

(X)

FRACTIONAL

DIVISION (K)

INTEGER

DIVISION (N)

2.048MHz

98.304MHz

12x4*

4.096MHz

98.304MHz

6x4*

12.288MHz

98.304MHz

13MHz

98.304MHz

7.5618

0.5618

27MHz (13.5MHz)**

98.304MHz

7.2818

0.2818

*Divide by 4 enabled in PLL feedback path for low frequency inputs. (LF = 1)

**Divide by 2 enabled at PLL input for frequencies > 14.4MHz > 38MHz (DIVSEL = 1, DIVCTL = 0)

Table 4 PLL Modes of Operation

PLL REGISTER PAGE ADDRESS MAPPING

The clock division control bits SPLL[6:0] and the PLL fractional N division bits are accessed through

words to be accessed whilst the register address is set to 46h. This means that when register

address 46h is selected a further 7 cycles of programming are required to set all of the page data

bits. Control bit allocation for these page addresses is described in Table 5.

PAGE

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

111

31:28

SPLL[6:4]

110

27:24

SPLL[3:0]

Clock division control bus SPLL[6:0]. Clock

divider reads this control word if PLL is

enabled

23:22

SPARE

Spare control bits

101

21:20

100

19:16

011

15:12

010

11:8

001

7:4

000

3:0

K[21:0]

Sigma Delta Modulator control word for

fractional N division. Division resolution is

1/22

Table 5 Pager Control Bit Allocation

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