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WM9713 数据表(PDF) 85 Page - Wolfson Microelectronics plc |
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WM9713 数据表(HTML) 85 Page - Wolfson Microelectronics plc |
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85 / 111 page ![]() Preliminary Technical Data WM9713L 1 PTD, March 2004, Rev 2.2 85 DATA SETUP AND HOLD Figure 29 Data Setup and Hold (50pF External Load) Note: Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9713L. PARAMETER SYMBOL MIN TYP MAX UNIT Setup to falling edge of BITCLK tSETUP 10 ns Hold from falling edge of BITCLK tHOLD 10 Ns Output valid delay from rising edge of BITCLK tCO 15 ns SIGNAL RISE AND FALL TIMES BITCLK SYNC SDATAIN SDATAOUT trise CLK tfall CLK trise SYNC tfall SYNC trise DIN tfall DIN trise DOUT tfall DOUT Figure 30 Signal Rise and Fall Times (50pF External Load) PARAMETER SYMBOL MIN TYP MAX UNIT BITCLK rise time triseCLK 2 6 ns BITCLK fall time tfallCLK 2 6 ns SYNC rise time triseSYNC 2 6 ns SYNC fall time tfallSYNC 2 6 ns SDATAIN rise time triseDIN 2 6 ns SDATAIN fall time tfallDIN 2 6 ns SDATAOUT rise time triseDOUT 2 6 ns SDATAOUT fall time tfallDOUT 2 6 ns |
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