STLC2500 datasheet(7/23 Pages) STMICROELECTRONICS

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STLC2500

(1)

Should be strapped to VSS_DIG if not used

(2)

Should be strapped to VDD_IO_A if not used

(3)

See also pin VDD_CLD in table 13

VDD_DIG

B02

Core logic supply

(Connect all to VDD_D)

C03

J02

J10

VDD_IO_A

F03

1.65V to 2.85V I/Os supply

(Connect all)

G02

G01

VDD_IO_B

K04

1.35V to 2.85V I/Os supply

VDD_CLD

G08

System clock supply

1.65V to 2.85V

(Connect all to VDD_IO_A in case of a

digital reference clock input, to

VSS_ANA in case of an analogue

reference clock input)

H09

VDD_DSM

E10

Internal supply decoupling

VDD_N

F10

Internal supply decoupling

VDD_CL

G10

Internal supply decoupling

VDD_RF

B05

Internal supply decoupling

VSS_DIG

A01

Digital ground

D03

E03

G03

H04

H05

H06

H07

H08

VSS_ANA

A02

Analogue ground

B03

B06

B09

B10

C04

C05

C07

C08

D08

E08

E09

F08

G09

VSS_RF

A04

RF ground

A07

Table 13. STLC2500 pin list (Functional and Supply) - continued

Name

Pin #

Description

DIR

Reset

Default

after reset

VDD_

IO_x

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