19/23

STLC2500

Table 22. PCM interface timing

Figure 8. PCM interface timing

8.3

The JTAG interface

The JTAG interface is compliant with the JTAG IEEE Standard 1149.1. It allows both the boundary scan

of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7

developments tools. It is also used for the industrial test of the device.

8.4

The GPIOs

The STLC2500 has 4 GPIO pins. They are fully programmable via specific HCI commands. They can be

configured as input, output, interrupt with asynchronous or synchronous edge or level detection and/or

wake-up.

Also other functions are multiplexed on the GPIO pins.

The alternative functions are

– WLAN co-existence control

– I2C interface

– PCM synchronization;

–GPIOs

Some functions are mutually exclusive, as per table 23.

Symbol

Description

Min.

Typ.

Max.

Unit

High period of PCM_CLK

200

ns

Low period of PCM_CLK

200

ns

High period of PCM_SYNC

200

ns

Setup time, PCM_SYNC high to PCM_CLK low

100

ns

Setup time, PCM_A/B input valid to PCM_CLK low

100

ns

Hold time, PCM_CLK low to PCM_A/B input valid

100

ns

Delay time, PCM_CLK high to PCM_A/B output valid

150

ns

MSB

MSB

MSB-1

MSB-1

MSB-2

MSB-2

MSB-3

MSB-3

PCM_CLK

PCM_SYNC

PCM_A/B in

PCM_A/B out