STLC2500

4/23

3.5

Current Consumption

4

BLOCK DIAGRAM AND ELECTRICAL SCHEMA

Figure 2. The complete chip

STLC2500 state

Value

Unit

Complete Power Down

6

µA

Deep Sleep Mode

25

µA

Sleep Mode

1.4

mA

Page/Inquiry scan (1,28 seconds period), combined with Deep Sleep Mode

0.4

mA

Active: audio (HV3)

10.9

mA

Active: data (DH1) (172,8 Kbps symmetrical)

21.8

mA

Active: audio eSCO (EV3), (64 Kbps symmetrical TSCO=6)

11.3

mA

Active: audio eSCO (EV5), (64 Kbps symmetrical TSCO=12)

9.6

mA

Active: audio eSCO (EV5), (64 Kbps symmetrical TSCO=18)

9.1

mA

Active: audio eSCO (EV5), (64 Kbps symmetrical TSCO=24)

8.9

mA

Active: audio eSCO (EV5), (64 Kbps symmetrical TSCO=36)

8.5

mA

Continuous RX, RF sub chip only.

34

mA

Continuous TX, RF sub chip only at 2.5 dBm output power.

32

mA

Transmitter

RF PLL

(FracN)

RFP

Sq.

RFN

Filter

2.5V

EMU

ARM7TDMI

CPU Wrapper

ROM

Timer

Receiver

Demo-

dulator

Auto Calib.

Internal Supply Management

2.75V

PLL

1.2V

EMU

RF_CLK_IN

RAM

UART

Interrupt

PCM

JTAG [4:0]

JTAG [4:0]

VDD_IO

(1.8-2.75V)

WLAN

Modu-

lator

HOST_WAKEUP

HOST_WAKEUP

LP_CLK

LP_CLK

BT_WAKEUP

BT_WAKEUP

RESETN

RESETN

UART [3:0]

UART [3:0]

CONFIG [4:0]

CONFIG [4:0]

GPIO [3:0]

GPIO [3:0]

PCM [3:0]

PCM [3:0]

Control

&

Registers

I2C

AMBA

Peripheral

Bus