STLC2500

12/23

7.2

Transmitter

All output power specifications are given at the pin level and over temperature range unless otherwise

specified.

7.3

System clock

The STLC2500 works with a single clock (sine wave or digital) provided on the RF_CLK_IN pin. Precision

of this clock should be 20 ppm. The external STLC2500 clock could be 13 or 26 MHz (for GSM applica-

tion), 19.2 MHz and 38.4 MHz (for 2.5 & 3G & CDMA platforms).

7.4

Low power clock

The low power clock is used by the baseband part as reference clock during the low power modes. It re-

quires an accuracy of 250ppm. The external STLC2500 clock, provided on the LP_CLK digital pin could

be 3.2 kHz, 16.384 kHz, 32 kHz and 32.768 kHz.

The low power clock must be available at all times.

7.5

Clock detection

The system and low power clocks can be either selected by specific HCI command or by integrated auto-

matic detection algorithm. The clock detection routine steps are:

Adjacent (+3MHz) interference

@ Input signal

strength = -67dBm

-44

dB

Adjacent (-3MHz) interference

@ Input signal

strength = -67dBm

-37

dB

Adjacent (

≥±4MHz) interference @ Input signal

strength = -67dBm

-46

dB

Receiver inter-modulation

IMD

Inter-modulation

Measured as defined in BT

test specification.

-35

dBm

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

RFout

Output frequency range

2402

2480

MHz

TXpout

Nominal Output power

@2402-2480 MHz

0

3

5

dBm

In-band spurious emission

FCC

FCC’s 20 dB BW

932

kHz

TX_SE2

Channel offset=2

-51

dBm

TX_SE3

Channel offset=3

-55

dBm

TX_SE4

Channel offset

≥4 (except 13)

-57

dBm

Initial carrier frequency tolerance (for an exact reference)

∆F

|f_TX-f0|

-75

75

kHz

Carrier Frequency Drift

|

∆f_p1|

One slot packet

25

kHz

|

∆f_p3|

Three slots packet

40

kHz

|

∆f_p5|

Five slots packet

40

kHz

Carrier Frequency Drift rate

|

∆f/50us|

Frequency drift rate

20

kHz/µs

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit