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STLC2500 数据表(PDF) 18 Page - STMicroelectronics |
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STLC2500 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 23 page ![]() STLC2500 18/23 Figure 6. Linear mode Figure 7. Multi-slot operation The PCM implementation supports from 1 up to 3 slots per frame with the following parameters: Table 21. PCM interface parameters Symbol Description Min. Typ. Max. Unit PCM Interface FPCM_CLK Frequency of PCM_CLK 140 4000 kHz FPCM_SYNC Frequency of PCM_SYNC 8 kHz Psync_delay Delay of the starting of the first slot 0 255 cycles Pclk_number Available PCM_CLK clock cycles 0 255 cycles Ss Slot starts (programmable for every slot) 0 255 cycles D Data size 8 16 bit N Number of slots per frame 1 3 0 1 15 PCM_CLK 125 µs PCM_SYNC PCM_A PCM_B 0 1 15 PCM_CLK 125 µs PCM_SYNC PCM_A PCM_B DATA SIZE P_SYNC_DELAY |
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