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STLC2500

5PINOUT

5.1

Pin out bottom view

5.2

Pin Description and Assignment

Table 13 shows the pin list of the STLC2500. The column "PU/PD" shows the pads implementing a pull-

down/up. The column "DIR" describes the pin directions:

– I for Inputs

– O for Outputs

– I/O for Input/Output

– O/t for tri-state outputs

The column Reset and Default show the state of the pins in reset and the default value after reset. For the

output pin the default drive capability is 2 mA.

Table 13. STLC2500 pin list (Functional and Supply)

Name

Pin #

Description

DIR

Reset

Default

after reset

VDD_

IO_x

Clock and Reset pins

RESETN

K03

Global reset - active low

I

Input

Input

A

RF_CLK_IN

H10

Reference clock input

I

Input

Input

(3)

LP_CLK

K05

Low power clock input

I

Input

Input

B

ABUS_

QP_IP

ANA_1

ABUS_

IN_QN

VSS_RF

RFN

RFP

VSS_RF

VDD_HV

VSS_ANA

VSS_DIG

VSS_ANA

VSS_ANA

ABUS_

QN_IN

ABUS_

IP_QP

VSS_ ANA

VDD_RF

ANA_2

VSS_ANA

VDD_DIG

JTAG_TDO

ANA_3

VSS_ANA

VSS_ANA

VDD_T

VSS_ANA

VSS_ANA

JTAG_

NTRST

JTAG_TDI

VDD_DSM

VSS_ANA

VSS_ANA

ANA_4

VSS_ANA

VSS_DIG

VSS_DIG

JTAG_TCK JTAG_TMS

PCM_SYNC PCM_CLK

VDD_N

VDD_HV

VSS_ANA

VDD_IO_A

PCM_A

PCM_B

VDD_CL

VSS_ANA

VDD_CLD

VSS_DIG

VDD_IO_A

VDD_IO_A

RF_CLK_IN

VDD_CLD

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

CONFIG

_R

CONFIG

_CLK

CONFIG

_JS

VDD_DIG

GPIO_2

GPIO_0

UART_

RXD

UART_

CTS

HOST_

WAKEUP

CONFIG

_RF

BT_

WAKEUP

VDD_DIG

CONFIG

_M

AF_PRG

GPIO_3

PGIO_1

UART_

TXD

UART_

RTS

LP_CLK

VDD_IO_B

RESETN

VDD_D

VDD_HV

VDD_HV

VDD_DIG

VDD_HV

A

B

C

D

E

F

G

H

J

K

10

9

8

7

6

5

4

3

2

1