DA14581_16 datasheet(108/153 Pages) DIALOG

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Datasheet

Revision 3.2

17-Jan-2017

CFR0011-120-01

108 of 153

DA14581

Bluetooth Low Energy 4.2 SoC with Optimized Boot Time

FINAL

Table 162: I2C_ACK_GENERAL_CALL_REG (0x50001398)

Bit

Mode

Symbol

Description

Reset

15:1

Reserved

0x0

r/w

ACK_GEN_CALL

ACK General Call. When set to 1, I2C Ctrl responds with a

ACK (by asserting ic_data_oe) when it receives a General

Call. When set to 0, the controller does not generate General

Call interrupts.

0x0

Table 163: I2C_ENABLE_STATUS_REG (0x5000139C)

Bit

Mode

Symbol

Description

Reset

15:3

Reserved

0x0

SLV_RX_DATA_LOS

Slave Received Data Lost. This bit indicates if a Slave-

Receiver

operation has been aborted with at least one data byte

received from an I2C transfer due to the setting of

IC_ENABLE from 1 to 0. When read as 1, the controller is

deemed to have been actively engaged in an aborted I2C

transfer (with matching address) and the data phase of the

I2C transfer has been entered, even though a data byte has

been responded with a NACK. NOTE: If the remote I2C mas-

ter terminates the transfer with a STOP condition before the

controller has a chance to NACK a transfer, and IC_ENABLE

has been set to 0, then this bit is also set to 1.

When read as 0, the controller is deemed to have been dis-

abled without being actively involved in the data phase of a

Slave-Receiver transfer.

NOTE: The CPU can safely read this bit when IC_EN (bit 0)

is read as 0.

0x0

SLV_DISABLED_WH

ILE_BUSY

Slave Disabled While Busy (Transmit, Receive). This bit indi-

cates if a potential or active Slave operation has been

aborted due to the setting of the IC_ENABLE register from 1

to 0. This bit is set when the CPU writes a 0 to the

IC_ENABLE register while:

(a) I2C Ctrl is receiving the address byte of the Slave-Trans-

mitter operation from a remote master; OR,

(b) address and data bytes of the Slave-Receiver operation

from a remote master. When read as 1, the controller is

deemed to have forced a NACK during any part of an I2C

transfer, irrespective of whether the I2C address matches

the slave address set in I2C Ctrl (IC_SAR register) OR if the

transfer is completed before IC_ENABLE is set to 0 but has

not taken effect.

NOTE: If the remote I2C master terminates the transfer with

a STOP condition before the the controller has a chance to

NACK a transfer, and IC_ENABLE has been set to 0, then

this bit will also be set to 1.

When read as 0, the controller is deemed to have been dis-

abled when there is master activity, or when the I2C bus is

idle.

NOTE: The CPU can safely read this bit when IC_EN (bit 0)

is read as 0.

0x0

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