FT313HP-R datasheet(38/67 Pages) FTDI

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Document No.: FT_000589

FT313H USB2.0 HS Host Controller Datasheet Version 1.2

Clearance No.: FTDI# 318

Bit

Name

Type

Default value

Description

REMOTEWKINT

_EN

Control the INT generation when the host

controller supports remote wake up

0: No INT will be generated when remote

wake up occurred.

1: INT will be asserted when remote wake up

occurred.

DMAEOTINT_EN

R/W

1’b0

DMA EOT interrupt enable

Control assertion of INT on the DMA transfer

completion

0: No INT will be generated when a DMA

transfer is completed.

1: INT will be asserted when a DMA transfer is

completed.

SOFINT_EN

R/W

1’b0

SOF interrupt enable

Control the INT generation at every SOF

occurrence

0: No INT will be generated on SOF.

1: INT will be asserted at every SOF.

MSOFINT_EN

R/W

1’b0

uSOF interrupt enable

Control the INT generation at every uSOF

occurrence

0: No INT will be generated on uSOF.

1: INT will be asserted at every uSOF.

Table 5-25 HC interrupt status register

5.5 USB testing registers

5.5.1 TESTMODE register (address = 50h)

This register allows the firmware to set the DP and DM pins to predetermined states for testing purposes.

Once force one test mode on host, must use test device on port connection.

Note: Only one bit can be set to logic 1 at a time. After writing to this register, need add 150ns delay

before writing this register again. The registers 70h and 74h both have same operation.

Bit

Name

Type

Default value

Description

[31:5]

Reserved

27’b0

TST_LOOPBK

R/W

1’b0

Turn on the loop back mode. When this bit is

set to ‘1’, the host controller will enter the loop

back mode.

Reserved

1’b0

TST_PKT

R/W

1’b0

TEST_PACKET

After entering the high speed and writing 1’b1

to this bit, users should command the DMA by

the test parameter setting registers (0x70h

and 0x74h) to move the packet data defined

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