AM29F016 datasheet(16/36 Pages) AMD

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Am29F016

DQ6

Toggle Bit I

The Am29F016 also features the “Toggle Bit I” as a

method to indicate to the host system that the embed-

ded algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cy-

cle, successive attempts to read (OE toggling) data

from the device

at any address will result in DQ6 tog-

gling between one and zero. Once the Embedded Pro-

gram or Erase Algorithm cycle is completed, DQ6 will

stop toggling and valid data will be read on

the next

successive attempts. During programming, the Toggle

Bit I is valid after the rising edge of the fourth WE pulse

in the four write pulse sequence. For chip erase, the

Toggle Bit I is valid after the rising edge of the sixth WE

pulse in the six write pulse sequence. For Sector

Erase, the Toggle Bit I is valid after the last rising edge

of the sector erase WE pulse. The Toggle Bit I is active

during the sector erase time out.

Either CE or OE toggling will cause the DQ6 to toggle.

In addition, an Erase Suspend/Resume command will

cause DQ6 to toggle. See Figure 12 for the Toggle Bit I

timing specifications and diagrams.

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has ex-

ceeded the specified limits (internal pulse count).

Under these conditions DQ5 will produce a “1”. This is

a failure condition which indicates that the program or

erase cycle was not successfully completed. Data Poll-

ing is the only operating function of the device under

this condition. The CE circuit will partially power down

the device under these conditions (to approximately 2

mA). The OE and WE pins will control the output dis-

able functions as described in Table 1.

The DQ5 failure condition will also appear if a user tries

to program a “1” to a location that is previously pro-

grammed to “0”. In this case the device locks out and

never completes the Embedded Program Algorithm.

Hence, the system never reads a valid data on DQ7 bit

and DQ6 never stops toggling. Once the device has ex-

ceeded timing limits, the DQ5 bit will indicate a “1.”

Please note that this is not a device failure condition

since the device was incorrectly used. If this occurs,

reset the device.

DQ3

Sector Erase Timer

After the completion of the initial sector erase com-

mand sequence the sector erase time-out will begin.

DQ3 will remain low until the time-out is complete. Data

Polling and Toggle Bit I are valid after the initial sector

erase command sequence.

If Data Polling or the Toggle Bit I indicates the device

has been written with a valid erase command, DQ3

may be used to determine if the sector erase timer win-

dow is still open. If DQ3 is high (“1”) the internally con-

trolled erase cycle has begun; attempts to write

subsequent commands (other than Erase Suspend) to

the device will be ignored until the erase operation is

completed as indicated by Data Polling or Toggle Bit I.

If DQ3 is low (“0”), the device will accept additional sec-

tor erase commands. To insure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 were high on the second sta-

tus check, the command may not have been accepted.

Refer to Table 6: Write Operation Status.

DQ2

Toggle Bit II

This toggle bit, along with DQ6, can be used to deter-

mine whether the device is in the Embedded Erase Al-

gorithm or in Erase Suspend.

Successive reads from the erasing sector will cause

DQ2 to toggle during the Embedded Erase Algorithm.

If the device is in the erase-suspended-read mode,

successive reads from the erase-suspend sector will

cause DQ2 to toggle. When the device is in the

erase-suspended-program mode, successive reads

from the byte address of the non-erase suspended sec-

tor will indicate a logic ‘1’ at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only

when the standard Program or Erase, or Erase Sus-

pend Program operation is in progress. The behavior of

these two status bits, along with that of DQ7, is summa-

rized as follows:

Notes:

1. These status flags apply when outputs are read from a

sector that has been erase-suspended.

2. These status flags apply when outputs are read from the

byte address of the non-erase suspended sector.

For example, DQ2 and DQ6 can be used together to

determine the erase-suspend-read mode (DQ2 toggles

while DQ6 does not). See also Table 6 and Figure 17.

Mode

DQ7

DQ6

DQ2

Program

DQ7

toggles

Erase

toggles

Erase Suspend Read (1)

(Erase-Suspended Sector)

toggles

Erase Suspend Program

DQ7 (2)

toggles

1 (2)

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