AM29F016 datasheet(17/36 Pages) AMD

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Am29F016

Furthermore, DQ2 can also be used to determine

which sector is being erased. When the device is in the

erase mode, DQ2 toggles if this bit is read from the

erasing sector.

RY/BY

Ready/Busy

The Am29F016 provides a RY/BY open-drain output

pin as a way to indicate to the host system that the Em-

bedded Algorithms are either in progress or has been

completed. If the output is low, the device is busy with

either a program or erase operation. If the output is

high, the device is ready to accept any read/write or

erase operation. When the RY/BY pin is low, the device

will not accept any additional program or erase com-

mands with the exception of the Erase Suspend com-

mand. If the Am29F016 is placed in an Erase Suspend

mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after

the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising

edge of the sixth WE pulse. The RY/BY pin will indicate

a busy condition during the RESET pulse. Refer to

Figure 13 for a detailed timing diagram. The RY/BY pin

is pulled high in standby mode.

Since this is an open-drain output, several RY/BY pins

can be tied together in parallel with a pull-up resistor

to VCC.

RESET

Hardware Reset

The Am29F016 device may be reset by driving the

RESET pin to VIL. The RESET pin must be kept low

(VIL) for at least 500 ns. Any operation in progress will

be terminated and the internal state machine will be

reset to the read mode 20

µs after the RESET pin is

driven low. If a hardware reset occurs during a pro-

gram operation, the data at that particular location will

be indeterminate.

When the RESET pin is low and the internal reset is

complete, the device goes to standby mode and cannot

be accessed. Also, note that all the data output pins are

tri-stated for the duration of the RESET pulse. Once the

RESET pin is taken high, the device requires 500 ns of

wake up time until outputs are valid for read access.

The RESET pin may be tied to the system reset input.

Therefore, if a system reset occurs during the Embed-

ded Program or Erase Algorithm, the device will be au-

tomatically reset to read mode and this will enable the

system’s microprocessor to read the boot-up firmware

from the Flash memory.

Data Protection

The Am29F016 is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tions. During power up the device automatically resets

the internal state machine in the Read mode. Also, with

its control register architecture, alteration of the mem-

ory contents only occurs after successful completion of

specific multi-bus cycle command sequences.

The device also incorporates several features to pre-

vent inadvertent write cycles resulting from VCC

power-up and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and power-down, a write cycle is locked out for VCC

less than 3.2 V (typically 3.7 V). If VCC < VLKO, the com-

mand register is disabled and all internal program/

erase circuits are disabled. Under this condition the de-

vice will reset to the read mode. Subsequent writes will

be ignored until the VCC level is greater than VLKO. It is

the user’s responsibility to ensure that the control pins

are logically correct to prevent unintentional writes

when VCC is above 3.2 V.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE or

WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL,

CE = VIH or WE = VIH. To initiate a write cycle CE and

WE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and

OE = VIH will not accept commands on the rising

edge of WE. The internal state machine is auto-

matically reset to the read mode on power-up.

AM29F016 数据表(PDF) 17 Page - Advanced Micro Devices

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