Am29F016

19

EMBEDDED ALGORITHMS

Figure 2.

Embedded Erase Algorithm

Start

Erasure Completed

Write Erase Command Sequence

(see below)

Data Polling or Toggle Bit I

Successfully Completed

5555H/AAH

2AAAH/55H

5555H/80H

Chip Erase Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/10H

5555H/AAH

2AAAH/55H

5555H/80H

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

5555H/AAH

Sector Address/30H

Sector Address/30H

Sector Address/30H

2AAAH/55H

Additional sector

erase commands

are optional

18805C-7

To insure the command has been accepted, the system software should check the status of DQ3 prior to and following

each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have

been accepted.