TNETV2685FIBZUT7 datasheet(23/191 Pages) TI1

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TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

Table 2-4. Terminal Functions (continued)

TERMINAL NAME

TYPE(

INTERNAL

OPER

DESCRIPTION

PULLUP/

VOLT

PULLDOWN

DDR_D16

B16

I/O/Z

1.8 V

DDR2 Memory Controller External Data (continued)

DDR_D17

C16

I/O/Z

1.8 V

DDR_D18

D16

I/O/Z

1.8 V

DDR_D19

E16

I/O/Z

1.8 V

DDR_D20

B17

I/O/Z

1.8 V

DDR_D21

C17

I/O/Z

1.8 V

DDR_D22

D17

I/O/Z

1.8 V

DDR_D23

E17

I/O/Z

1.8 V

DDR_D24

C18

I/O/Z

1.8 V

DDR_D25

D18

I/O/Z

1.8 V

DDR_D26

B19

I/O/Z

1.8 V

DDR_D27

C19

I/O/Z

1.8 V

DDR_D28

B20

I/O/Z

1.8 V

DDR_D29

D19

I/O/Z

1.8 V

DDR_D30

C20

I/O/Z

1.8 V

DDR_D31

E19

I/O/Z

1.8 V

DDR_ODT0

E13

I/O/Z

1.8 V

On-die termination signals to external DDR2 SDRAM. These pins

are reserved for future use and should not be connected to the

DDR_ODT1

A14

I/O/Z

1.8 V

DDR2 SDRAM.

Note: There are no on-die termination resistors implemented on

the DM647/DM648 DSP die.

DDR_CAS

D10

I/O/Z

1.8 V

DDR2 Memory Controller SDRAM column address strobe

DDR_CKE

B11

I/O/Z

1.8 V

DDR2 Memory Controller SDRAM clock-enable

DDR_DQGATE0

I/O/Z

1.8 V

DDR2 Memory Controller Data Strobe Gate

DDR_DQGATE1

I/O/Z

1.8 V

DDR_DQGATE2

E18

I/O/Z

1.8 V

DDR_DQGATE3

A21

I/O/Z

1.8 V

DDR_DQM[0]

I/O/Z

1.8 V

DDR2 Memory Controller Byte-enable Controls. Decoded from the

low-order address bits. The number of address bits or byte

DDR_DQM[1]

I/O/Z

1.8 V

enables used depends on the width of external memory. Byte-write

DDR_DQM[2]

E15

I/O/Z

1.8 V

enables for most types of memory. Can be directly connected to

SDRAM read and write mask signal (SDQM).

DDR_DQM[3]

B21

I/O/Z

1.8 V

DDR_DQS[0]

I/O/Z

1.8 V

DDR2 Memory Controller Data Strobe [3:0]

DDR_DQS[1]

I/O/Z

1.8 V

DDR_DQS[2]

A17

I/O/Z

1.8 V

DDR_DQS[3]

A20

I/O/Z

1.8 V

DDR_DQS[0]

I/O/Z

1.8 V

DDR2 Memory Controller Data Strobe [3:0] Negative

DDR_DQS[1]

I/O/Z

1.8 V

DDR_DQS[2]

A16

I/O/Z

1.8 V

DDR_DQS[3]

A19

I/O/Z

1.8 V

DDR_RAS

E10

I/O/Z

1.8 V

DDR2 Memory Controller SDRAM Row Address Strobe

DDR_WE

D11

I/O/Z

1.8 V

DDR2 Memory Controller SDRAM Write Enable

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