TNETV2685FIBZUT7 datasheet(9/191 Pages) TI1

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TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

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Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common

instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+

compiler can restrict the code to use certain registers in the register file. This compression is

performed by the code generation tools.

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Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit

multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field

multiplication.

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Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to

detect and respond to exceptions, both from internally detected sources (such as illegal opcodes).

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Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a

basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with

read, write, and execute permissions.

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Time-Stamp Counter - Primarily targeted for real-time operating system (RTOS) robustness, a free-

running time-stamp counter that is not sensitive to system stalls is implemented in the CPU.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following

documents:

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TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)

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TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871)

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TMS320C64x to TMS320C64x+ CPU Migration Guide Application Report (literature number SPRAA84)

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TMS320C64x+ DSP Cache User's Guide (literature number SPRU862)

Device Overview

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